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tegra: hwpm: t264: Enable VI and ISP compilation
Enable Camera (VI and ISP) IP file compilation in HWPM driver for AV+L builds only. Bug 4345706 Signed-off-by: vasukis <vasukis@nvidia.com> Change-Id: If647e7e25ce7d1a853cc7c298780538e03392ec0 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3283197 Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Yifei Wan <ywan@nvidia.com>
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@@ -1,6 +1,6 @@
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# -*- mode: makefile -*-
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#
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# Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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@@ -88,4 +88,10 @@ nvhwpm-t264-objs += hal/t264/ip/ucf_csw/t264_ucf_csw.o
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ccflags-y += -DCONFIG_T264_HWPM_IP_CPU
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nvhwpm-t264-objs += hal/t264/ip/cpu/t264_cpu.o
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ccflags-y += -DCONFIG_T264_HWPM_IP_VI
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nvhwpm-t264-objs += hal/t264/ip/vi/t264_vi.o
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ccflags-y += -DCONFIG_T264_HWPM_IP_ISP
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nvhwpm-t264-objs += hal/t264/ip/isp/t264_isp.o
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endif
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@@ -80,12 +80,6 @@ int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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#endif
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#if defined(CONFIG_T264_HWPM_IP_CPU)
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case T264_HWPM_IP_CPU:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_VI)
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case T264_HWPM_IP_VI:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_ISP)
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case T264_HWPM_IP_ISP:
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#endif
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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@@ -97,6 +91,32 @@ int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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goto fail;
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}
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break;
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#if defined(CONFIG_T264_HWPM_IP_VI)
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case T264_HWPM_IP_VI:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_ISP)
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case T264_HWPM_IP_ISP:
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#endif
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if (tegra_hwpm_is_hypervisor_mode()) {
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/*
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* VI and ISP are enabled only on AV+L configuration
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* as the camera driver is not supported on L4T.
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*/
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"Failed to %s fs/ops for IP %d (base 0x%llx)",
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available == true ? "set" : "reset",
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ip_idx, (unsigned long long)base_address);
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goto fail;
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}
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} else {
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tegra_hwpm_err(hwpm, "Invalid IP %d for ip_ops", ip_idx);
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}
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break;
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#if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
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case T264_HWPM_IP_MSS_CHANNEL:
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#endif
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: MIT
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -224,10 +224,18 @@ struct allowlist t264_cpucore_alist[4] = {
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{0x00000018, true},
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};
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struct allowlist t264_vi_alist[1] = {
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{0x0000c004, true},
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struct allowlist t264_vi_alist[5] = {
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{0x00030008, true},
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{0x0003000c, true},
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{0x00030010, true},
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{0x00030014, true},
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{0x00030018, true},
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};
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struct allowlist t264_isp_alist[1] = {
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{0x0000c004, true},
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struct allowlist t264_isp_alist[5] = {
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{0x00030008, true},
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{0x0003000c, true},
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{0x00030010, true},
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{0x00030014, true},
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{0x00030018, true},
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};
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -43,7 +43,7 @@ extern struct allowlist t264_ucf_msw_slc_alist[1];
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extern struct allowlist t264_ucf_psn_psw_alist[2];
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extern struct allowlist t264_ucf_csw_alist[2];
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extern struct allowlist t264_cpucore_alist[4];
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extern struct allowlist t264_vi_alist[1];
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extern struct allowlist t264_isp_alist[1];
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extern struct allowlist t264_vi_alist[5];
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extern struct allowlist t264_isp_alist[5];
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#endif /* T264_HWPM_REGOPS_ALLOWLIST_H */
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