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tegra: hwpm: t264: Fix VI and ISP ip details

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VI and ISP (Camera modules) have an overlapping MMIO
address regions with both overlapping. Hence, set the
islots_overlimit flag to indicate this in HWPM driver.

Fix minor errors in VI and ISP driver enablement in HWPM
driver.

Bug 5072985

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: I37d84c1ae6750202abd8caa9adb38a79f8b75537
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3323540
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
This commit is contained in:
vasukis
2025-03-20 22:04:47 +00:00
committed by mobile promotions
parent 742e79fa06
commit a02386ec6e
4 changed files with 8 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/tegra/hwpm/hal/t264/ip/isp/t264_isp.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -265,6 +265,7 @@ struct hwpm_ip t264_hwpm_ip_isp = {
.inst_stride = addr_map_isp_thi_limit_r() -
addr_map_isp_thi_base_r() + 1ULL,
.inst_slots = 0U,
.islots_overlimit = true,
.inst_arr = NULL,
},
/*

3
drivers/tegra/hwpm/hal/t264/ip/vi/t264_vi.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -265,6 +265,7 @@ struct hwpm_ip t264_hwpm_ip_vi = {
.inst_stride = addr_map_vi_thi_limit_r() -
addr_map_vi_thi_base_r() + 1ULL,
.inst_slots = 0U,
.islots_overlimit = true,
.inst_arr = NULL,
},
/*

2
drivers/tegra/hwpm/hal/t264/t264_interface.c
View File

@@ -242,7 +242,7 @@ bool t264_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
#endif
break;
#if defined(CONFIG_T264_HWPM_IP_ISP)
case TEGRA_HWPM_IP_ISP:
case TEGRA_HWPM_RESOURCE_ISP:
config_ip = T264_HWPM_IP_ISP;
#endif
break;

6
drivers/tegra/hwpm/hal/t264/t264_internal.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -47,6 +47,8 @@
#define T264_ACTIVE_IPS \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_PMA) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_RTR) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_VI) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_ISP) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_VIC) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_PVA) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_MSS_CHANNEL) \
@@ -57,8 +59,6 @@
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_UCF_PSW) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_UCF_CSW) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_CPU) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_VI) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_ISP) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_MAX)
enum t264_hwpm_active_ips {