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tegra: hwpm: Add OPT_HWPM_DISABLE mask definition

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- Add OPT_HWPM_DISABLE fuse (offset 0xd18) mask for NEXT3
chip.

Jira THWPM-73

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: Idc403276886fb2f00b18a69be2c285bc8b3da000
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3139627
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
vasukis
2024-05-16 20:16:56 +00:00
committed by mobile promotions
parent 5f4378574c
commit ab110e5f27
1 changed files with 2 additions and 1 deletions
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3
drivers/tegra/hwpm/include/tegra_hwpm.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */ /* SPDX-License-Identifier: MIT */
/* /*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -39,6 +39,7 @@
#define TEGRA_HWPM_FUSE_PRODUCTION_MODE_MASK BIT(0) #define TEGRA_HWPM_FUSE_PRODUCTION_MODE_MASK BIT(0)
#define TEGRA_HWPM_FUSE_SECURITY_MODE_MASK BIT(1) #define TEGRA_HWPM_FUSE_SECURITY_MODE_MASK BIT(1)
#define TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK BIT(2) #define TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK BIT(2)
#define TEGRA_HWPM_FUSE_OPT_HWPM_DISABLE_MASK BIT(3)
/* Indicate the prescence of HWPM-IP debug interface for devctl calls */ /* Indicate the prescence of HWPM-IP debug interface for devctl calls */
#define TEGRA_HWPM_IP_DEBUG_FD_INVALID -1 #define TEGRA_HWPM_IP_DEBUG_FD_INVALID -1