tegra: hwpm: th500: Add support for C-NVLINK

This patch adds support for C-NVLINK performance
monitoring in the driver. C-NVLINK consists of
RX, TX, and CTRL apertures, each with its own
perfmux signals and perfmons. So this patch
breaks them up into three sets of perfmux-perfmon
data structures.

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: Id8be4c965018125765f75a7b8bc8ab809bb7f976
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2999166
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>

drivers/tegra/hwpm/Makefile.th500.soc.sources

@@ -49,4 +49,9 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/smmu/th500_smmu.o
 ccflags-y += -DCONFIG_TH500_HWPM_IP_CL2
 nvhwpm-th500-soc-objs += hal/th500/soc/ip/cl2/th500_cl2.o
 
+ccflags-y += -DCONFIG_TH500_HWPM_IP_C_NVLINK
+nvhwpm-th500-soc-objs += hal/th500/soc/ip/c_nvlink/th500_nvlrx.o
+nvhwpm-th500-soc-objs += hal/th500/soc/ip/c_nvlink/th500_nvltx.o
+nvhwpm-th500-soc-objs += hal/th500/soc/ip/c_nvlink/th500_nvlctrl.o
+
 endif

drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h

@@ -366,10 +366,66 @@
 #define addr_map_rpg_pm_nvlctrl0_limit_r()                         (0x13e8bfffU)
 #define addr_map_rpg_pm_nvlctrl1_base_r()                          (0x13e8c000U)
 #define addr_map_rpg_pm_nvlctrl1_limit_r()                         (0x13e8cfffU)
-#define addr_map_nvlw0_base_r()                                    (0x03b80000U)
+#define addr_map_nvlw0_ctrl_base_r()                               (0x03b80000U)
-#define addr_map_nvlw0_limit_r()                                   (0x03bbffffU)
+#define addr_map_nvlw0_ctrl_limit_r()                              (0x03b81fffU)
-#define addr_map_nvlw1_base_r()                                    (0x03bc0000U)
+#define addr_map_nvlw1_ctrl_base_r()                               (0x03bc0000U)
-#define addr_map_nvlw1_limit_r()                                   (0x03bfffffU)
+#define addr_map_nvlw1_ctrl_limit_r()                              (0x03bc1fffU)
+#define addr_map_nvlw0_nvldl0_base_r()                             (0x03b90000U)
+#define addr_map_nvlw0_nvldl0_limit_r()                            (0x03b94fffU)
+#define addr_map_nvlw0_nvltlc0_base_r()                            (0x03b95000U)
+#define addr_map_nvlw0_nvltlc0_limit_r()                           (0x03b96fffU)
+#define addr_map_nvlw0_nvldl1_base_r()                             (0x03b98000U)
+#define addr_map_nvlw0_nvldl1_limit_r()                            (0x03b9cfffU)
+#define addr_map_nvlw0_nvltlc1_base_r()                            (0x03b9d000U)
+#define addr_map_nvlw0_nvltlc1_limit_r()                           (0x03b9efffU)
+#define addr_map_nvlw0_nvldl2_base_r()                             (0x03ba0000U)
+#define addr_map_nvlw0_nvldl2_limit_r()                            (0x03ba4fffU)
+#define addr_map_nvlw0_nvltlc2_base_r()                            (0x03ba5000U)
+#define addr_map_nvlw0_nvltlc2_limit_r()                           (0x03ba6fffU)
+#define addr_map_nvlw0_nvldl3_base_r()                             (0x03ba8000U)
+#define addr_map_nvlw0_nvldl3_limit_r()                            (0x03bacfffU)
+#define addr_map_nvlw0_nvltlc3_base_r()                            (0x03bad000U)
+#define addr_map_nvlw0_nvltlc3_limit_r()                           (0x03baefffU)
+#define addr_map_nvlw0_nvldl4_base_r()                             (0x03bb0000U)
+#define addr_map_nvlw0_nvldl4_limit_r()                            (0x03bb4fffU)
+#define addr_map_nvlw0_nvltlc4_base_r()                            (0x03bb5000U)
+#define addr_map_nvlw0_nvltlc4_limit_r()                           (0x03bb6fffU)
+#define addr_map_nvlw0_nvldl5_base_r()                             (0x03bb8000U)
+#define addr_map_nvlw0_nvldl5_limit_r()                            (0x03bbcfffU)
+#define addr_map_nvlw0_nvltlc5_base_r()                            (0x03bbd000U)
+#define addr_map_nvlw0_nvltlc5_limit_r()                           (0x03bbefffU)
+#define addr_map_nvlw1_nvldl0_base_r()                             (0x03bd0000U)
+#define addr_map_nvlw1_nvldl0_limit_r()                            (0x03bd4fffU)
+#define addr_map_nvlw1_nvltlc0_base_r()                            (0x03bd5000U)
+#define addr_map_nvlw1_nvltlc0_limit_r()                           (0x03bd6fffU)
+#define addr_map_nvlw1_nvldl1_base_r()                             (0x03bd8000U)
+#define addr_map_nvlw1_nvldl1_limit_r()                            (0x03bdcfffU)
+#define addr_map_nvlw1_nvltlc1_base_r()                            (0x03bdd000U)
+#define addr_map_nvlw1_nvltlc1_limit_r()                           (0x03bdefffU)
+#define addr_map_nvlw1_nvldl2_base_r()                             (0x03be0000U)
+#define addr_map_nvlw1_nvldl2_limit_r()                            (0x03be4fffU)
+#define addr_map_nvlw1_nvltlc2_base_r()                            (0x03be5000U)
+#define addr_map_nvlw1_nvltlc2_limit_r()                           (0x03be6fffU)
+#define addr_map_nvlw1_nvldl3_base_r()                             (0x03be8000U)
+#define addr_map_nvlw1_nvldl3_limit_r()                            (0x03becfffU)
+#define addr_map_nvlw1_nvltlc3_base_r()                            (0x03bed000U)
+#define addr_map_nvlw1_nvltlc3_limit_r()                           (0x03beefffU)
+#define addr_map_nvlw1_nvldl4_base_r()                             (0x03bf0000U)
+#define addr_map_nvlw1_nvldl4_limit_r()                            (0x03bf4fffU)
+#define addr_map_nvlw1_nvltlc4_base_r()                            (0x03bf5000U)
+#define addr_map_nvlw1_nvltlc4_limit_r()                           (0x03bf6fffU)
+#define addr_map_nvlw1_nvldl5_base_r()                             (0x03bf8000U)
+#define addr_map_nvlw1_nvldl5_limit_r()                            (0x03bfcfffU)
+#define addr_map_nvlw1_nvltlc5_base_r()                            (0x03bfd000U)
+#define addr_map_nvlw1_nvltlc5_limit_r()                           (0x03bfefffU)
+#define addr_map_nvlw0_nvldl_multi_base_r()                        (0x03b88000U)
+#define addr_map_nvlw0_nvldl_multi_limit_r()                       (0x03b8cfffU)
+#define addr_map_nvlw0_nvltlc_multi_base_r()                       (0x03b8d000U)
+#define addr_map_nvlw0_nvltlc_multi_limit_r()                      (0x03b8efffU)
+#define addr_map_nvlw1_nvldl_multi_base_r()                        (0x03bc8000U)
+#define addr_map_nvlw1_nvldl_multi_limit_r()                       (0x03bccfffU)
+#define addr_map_nvlw1_nvltlc_multi_base_r()                       (0x03bcd000U)
+#define addr_map_nvlw1_nvltlc_multi_limit_r()                      (0x03bcefffU)
 #define addr_map_rpg_pm_xalrc0_base_r()                            (0x13e00000U)
 #define addr_map_rpg_pm_xalrc0_limit_r()                           (0x13e00fffU)
 #define addr_map_rpg_pm_xalrc1_base_r()                            (0x13e01000U)

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlctrl.c

@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: MIT
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This is a generated file. Do not edit.
+ *
+ * Steps to regenerate:
+ *     python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
+ */
+
+#include "th500_nvlctrl.h"
+
+#include <tegra_hwpm.h>
+#include <hal/th500/soc/th500_soc_perfmon_device_index.h>
+#include <hal/th500/soc/th500_soc_regops_allowlist.h>
+#include <hal/th500/soc/hw/th500_addr_map_soc_hwpm.h>
+
+static struct hwpm_ip_aperture th500_nvlctrl_inst0_perfmon_element_static_array[
+	TH500_HWPM_IP_NVLCTRL_NUM_PERFMON_PER_INST] = {
+	{
+		.element_type = HWPM_ELEMENT_PERFMON,
+		.element_index_mask = BIT(0),
+		.element_index = 0U,
+		.dt_mmio = NULL,
+		.name = "perfmon_nvlctrl0",
+		.device_index = TH500_NVLCTRL0_PERFMON_DEVICE_NODE_INDEX,
+		.start_abs_pa = addr_map_rpg_pm_nvlctrl0_base_r(),
+		.end_abs_pa = addr_map_rpg_pm_nvlctrl0_limit_r(),
+		.start_pa = addr_map_rpg_pm_nvlctrl0_base_r(),
+		.end_pa = addr_map_rpg_pm_nvlctrl0_limit_r(),
+		.base_pa = addr_map_rpg_pm_base_r(),
+		.alist = th500_perfmon_alist,
+		.alist_size = ARRAY_SIZE(th500_perfmon_alist),
+		.fake_registers = NULL,
+	},
+};
+
+static struct hwpm_ip_aperture th500_nvlctrl_inst1_perfmon_element_static_array[
+	TH500_HWPM_IP_NVLCTRL_NUM_PERFMON_PER_INST] = {
+	{
+		.element_type = HWPM_ELEMENT_PERFMON,
+		.element_index_mask = BIT(0),
+		.element_index = 0U,
+		.dt_mmio = NULL,
+		.name = "perfmon_nvlctrl1",
+		.device_index = TH500_NVLCTRL1_PERFMON_DEVICE_NODE_INDEX,
+		.start_abs_pa = addr_map_rpg_pm_nvlctrl1_base_r(),
+		.end_abs_pa = addr_map_rpg_pm_nvlctrl1_limit_r(),
+		.start_pa = addr_map_rpg_pm_nvlctrl1_base_r(),
+		.end_pa = addr_map_rpg_pm_nvlctrl1_limit_r(),
+		.base_pa = addr_map_rpg_pm_base_r(),
+		.alist = th500_perfmon_alist,
+		.alist_size = ARRAY_SIZE(th500_perfmon_alist),
+		.fake_registers = NULL,
+	},
+};
+
+static struct hwpm_ip_aperture th500_nvlctrl_inst0_perfmux_element_static_array[
+	TH500_HWPM_IP_NVLCTRL_NUM_PERFMUX_PER_INST] = {
+	{
+		.element_type = IP_ELEMENT_PERFMUX,
+		.element_index_mask = BIT(0),
+		.element_index = 0U,
+		.dt_mmio = NULL,
+		.name = {'\0'},
+		.start_abs_pa = addr_map_nvlw0_ctrl_base_r(),
+		.end_abs_pa = addr_map_nvlw0_ctrl_limit_r(),
+		.start_pa = addr_map_nvlw0_ctrl_base_r(),
+		.end_pa = addr_map_nvlw0_ctrl_limit_r(),
+		.base_pa = 0ULL,
+		.alist = th500_nvlctrl_alist,
+		.alist_size = ARRAY_SIZE(th500_nvlctrl_alist),
+		.fake_registers = NULL,
+	},
+};
+
+static struct hwpm_ip_aperture th500_nvlctrl_inst1_perfmux_element_static_array[
+	TH500_HWPM_IP_NVLCTRL_NUM_PERFMUX_PER_INST] = {
+	{
+		.element_type = IP_ELEMENT_PERFMUX,
+		.element_index_mask = BIT(0),
+		.element_index = 0U,
+		.dt_mmio = NULL,
+		.name = {'\0'},
+		.start_abs_pa = addr_map_nvlw1_ctrl_base_r(),
+		.end_abs_pa = addr_map_nvlw1_ctrl_limit_r(),
+		.start_pa = addr_map_nvlw1_ctrl_base_r(),
+		.end_pa = addr_map_nvlw1_ctrl_limit_r(),
+		.base_pa = 0ULL,
+		.alist = th500_nvlctrl_alist,
+		.alist_size = ARRAY_SIZE(th500_nvlctrl_alist),
+		.fake_registers = NULL,
+	},
+};
+
+/* IP instance array */
+static struct hwpm_ip_inst th500_nvlctrl_inst_static_array[
+	TH500_HWPM_IP_NVLCTRL_NUM_INSTANCES] = {
+	{
+		.hw_inst_mask = BIT(0),
+		.num_core_elements_per_inst =
+			TH500_HWPM_IP_NVLCTRL_NUM_CORE_ELEMENT_PER_INST,
+		.element_info = {
+			/*
+			 * Instance info corresponding to
+			 * TEGRA_HWPM_APERTURE_TYPE_PERFMUX
+			 */
+			{
+				.num_element_per_inst =
+					TH500_HWPM_IP_NVLCTRL_NUM_PERFMUX_PER_INST,
+				.element_static_array =
+					th500_nvlctrl_inst0_perfmux_element_static_array,
+				/* NOTE: range should be in ascending order */
+				.range_start = addr_map_nvlw0_ctrl_base_r(),
+				.range_end = addr_map_nvlw0_ctrl_limit_r(),
+				.element_stride = addr_map_nvlw0_ctrl_limit_r() -
+					addr_map_nvlw0_ctrl_base_r() + 1ULL,
+				.element_slots = 0U,
+				.element_arr = NULL,
+			},
+			/*
+			 * Instance info corresponding to
+			 * TEGRA_HWPM_APERTURE_TYPE_BROADCAST
+			 */
+			{
+				.num_element_per_inst =
+					TH500_HWPM_IP_NVLCTRL_NUM_BROADCAST_PER_INST,
+				.element_static_array = NULL,
+				.range_start = 0ULL,
+				.range_end = 0ULL,
+				.element_stride = 0ULL,
+				.element_slots = 0U,
+				.element_arr = NULL,
+			},
+			/*
+			 * Instance info corresponding to
+			 * TEGRA_HWPM_APERTURE_TYPE_PERFMON
+			 */
+			{
+				.num_element_per_inst =
+					TH500_HWPM_IP_NVLCTRL_NUM_PERFMON_PER_INST,
+				.element_static_array =
+					th500_nvlctrl_inst0_perfmon_element_static_array,
+				.range_start = addr_map_rpg_pm_nvlctrl0_base_r(),
+				.range_end = addr_map_rpg_pm_nvlctrl0_limit_r(),
+				.element_stride = addr_map_rpg_pm_nvlctrl0_limit_r() -
+					addr_map_rpg_pm_nvlctrl0_base_r() + 1ULL,
+				.element_slots = 0U,
+				.element_arr = NULL,
+			},
+		},
+
+		.ip_ops = {
+			.ip_dev = NULL,
+			.hwpm_ip_pm = NULL,
+			.hwpm_ip_reg_op = NULL,
+			.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
+		},
+
+		.element_fs_mask = 0U,
+		.dev_name = "",
+	},
+	{
+		.hw_inst_mask = BIT(1),
+		.num_core_elements_per_inst =
+			TH500_HWPM_IP_NVLCTRL_NUM_CORE_ELEMENT_PER_INST,
+		.element_info = {
+			/*
+			 * Instance info corresponding to
+			 * TEGRA_HWPM_APERTURE_TYPE_PERFMUX
+			 */
+			{
+				.num_element_per_inst =
+					TH500_HWPM_IP_NVLCTRL_NUM_PERFMUX_PER_INST,
+				.element_static_array =
+					th500_nvlctrl_inst1_perfmux_element_static_array,
+				/* NOTE: range should be in ascending order */
+				.range_start = addr_map_nvlw1_ctrl_base_r(),
+				.range_end = addr_map_nvlw1_ctrl_limit_r(),
+				.element_stride = addr_map_nvlw1_ctrl_limit_r() -
+					addr_map_nvlw1_ctrl_base_r() + 1ULL,
+				.element_slots = 0U,
+				.element_arr = NULL,
+			},
+			/*
+			 * Instance info corresponding to
+			 * TEGRA_HWPM_APERTURE_TYPE_BROADCAST
+			 */
+			{
+				.num_element_per_inst =
+					TH500_HWPM_IP_NVLCTRL_NUM_BROADCAST_PER_INST,
+				.element_static_array = NULL,
+				.range_start = 0ULL,
+				.range_end = 0ULL,
+				.element_stride = 0ULL,
+				.element_slots = 0U,
+				.element_arr = NULL,
+			},
+			/*
+			 * Instance info corresponding to
+			 * TEGRA_HWPM_APERTURE_TYPE_PERFMON
+			 */
+			{
+				.num_element_per_inst =
+					TH500_HWPM_IP_NVLCTRL_NUM_PERFMON_PER_INST,
+				.element_static_array =
+					th500_nvlctrl_inst1_perfmon_element_static_array,
+				.range_start = addr_map_rpg_pm_nvlctrl1_base_r(),
+				.range_end = addr_map_rpg_pm_nvlctrl1_limit_r(),
+				.element_stride = addr_map_rpg_pm_nvlctrl1_limit_r() -
+					addr_map_rpg_pm_nvlctrl1_base_r() + 1ULL,
+				.element_slots = 0U,
+				.element_arr = NULL,
+			},
+		},
+
+		.ip_ops = {
+			.ip_dev = NULL,
+			.hwpm_ip_pm = NULL,
+			.hwpm_ip_reg_op = NULL,
+			.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
+		},
+
+		.element_fs_mask = 0U,
+		.dev_name = "",
+	},
+};
+
+/* IP structure */
+struct hwpm_ip th500_hwpm_ip_nvlctrl = {
+	.num_instances = TH500_HWPM_IP_NVLCTRL_NUM_INSTANCES,
+	.ip_inst_static_array = th500_nvlctrl_inst_static_array,
+
+	.inst_aperture_info = {
+		/*
+		 * Instance info corresponding to
+		 * TEGRA_HWPM_APERTURE_TYPE_PERFMUX
+		 */
+		{
+			/* NOTE: range should be in ascending order */
+			.range_start = addr_map_nvlw0_ctrl_base_r(),
+			.range_end = addr_map_nvlw1_ctrl_limit_r(),
+			.inst_stride = addr_map_nvlw0_ctrl_limit_r() -
+				addr_map_nvlw0_ctrl_base_r() + 1ULL,
+			.inst_slots = 0U,
+			.inst_arr = NULL,
+		},
+		/*
+		 * Instance info corresponding to
+		 * TEGRA_HWPM_APERTURE_TYPE_BROADCAST
+		 */
+		{
+			.range_start = 0ULL,
+			.range_end = 0ULL,
+			.inst_stride = 0ULL,
+			.inst_slots = 0U,
+			.inst_arr = NULL,
+		},
+		/*
+		 * Instance info corresponding to
+		 * TEGRA_HWPM_APERTURE_TYPE_PERFMON
+		 */
+		{
+			.range_start = addr_map_rpg_pm_nvlctrl0_base_r(),
+			.range_end = addr_map_rpg_pm_nvlctrl1_limit_r(),
+			.inst_stride = addr_map_rpg_pm_nvlctrl0_limit_r() -
+				addr_map_rpg_pm_nvlctrl0_base_r() + 1ULL,
+			.inst_slots = 0U,
+			.inst_arr = NULL,
+		},
+	},
+
+	.dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK,
+	.override_enable = false,
+	.inst_fs_mask = 0U,
+	.resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID,
+	.reserved = false,
+};

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlctrl.h

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This is a generated file. Do not edit.
+ *
+ * Steps to regenerate:
+ *     python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
+ */
+
+#ifndef TH500_HWPM_IP_NVLCTRL_H
+#define TH500_HWPM_IP_NVLCTRL_H
+
+#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
+#define TH500_HWPM_ACTIVE_IP_NVLCTRL	TH500_HWPM_IP_NVLCTRL,
+
+/* This data should ideally be available in HW headers */
+#define TH500_HWPM_IP_NVLCTRL_NUM_INSTANCES               2U
+#define TH500_HWPM_IP_NVLCTRL_NUM_CORE_ELEMENT_PER_INST   1U
+#define TH500_HWPM_IP_NVLCTRL_NUM_PERFMON_PER_INST        1U
+#define TH500_HWPM_IP_NVLCTRL_NUM_PERFMUX_PER_INST        1U
+#define TH500_HWPM_IP_NVLCTRL_NUM_BROADCAST_PER_INST      0U
+
+extern struct hwpm_ip th500_hwpm_ip_nvlctrl;
+
+#else
+#define TH500_HWPM_ACTIVE_IP_NVLCTRL
+#endif
+
+#endif /* TH500_HWPM_IP_NVLCTRL_H */

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlrx.h

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This is a generated file. Do not edit.
+ *
+ * Steps to regenerate:
+ *     python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
+ */
+
+#ifndef TH500_HWPM_IP_NVLRX_H
+#define TH500_HWPM_IP_NVLRX_H
+
+#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
+#define TH500_HWPM_ACTIVE_IP_NVLRX	TH500_HWPM_IP_NVLRX,
+
+/* This data should ideally be available in HW headers */
+#define TH500_HWPM_IP_NVLRX_NUM_INSTANCES               2U
+#define TH500_HWPM_IP_NVLRX_NUM_CORE_ELEMENT_PER_INST   6U
+#define TH500_HWPM_IP_NVLRX_NUM_PERFMON_PER_INST        12U
+#define TH500_HWPM_IP_NVLRX_NUM_PERFMUX_PER_INST        12U
+#define TH500_HWPM_IP_NVLRX_NUM_BROADCAST_PER_INST      2U
+
+extern struct hwpm_ip th500_hwpm_ip_nvlrx;
+
+#else
+#define TH500_HWPM_ACTIVE_IP_NVLRX
+#endif
+
+#endif /* TH500_HWPM_IP_NVLRX_H */

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvltx.h

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This is a generated file. Do not edit.
+ *
+ * Steps to regenerate:
+ *     python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
+ */
+
+#ifndef TH500_HWPM_IP_NVLTX_H
+#define TH500_HWPM_IP_NVLTX_H
+
+#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
+#define TH500_HWPM_ACTIVE_IP_NVLTX	TH500_HWPM_IP_NVLTX,
+
+/* This data should ideally be available in HW headers */
+#define TH500_HWPM_IP_NVLTX_NUM_INSTANCES               2U
+#define TH500_HWPM_IP_NVLTX_NUM_CORE_ELEMENT_PER_INST   6U
+#define TH500_HWPM_IP_NVLTX_NUM_PERFMON_PER_INST        12U
+#define TH500_HWPM_IP_NVLTX_NUM_PERFMUX_PER_INST        12U
+#define TH500_HWPM_IP_NVLTX_NUM_BROADCAST_PER_INST      2U
+
+extern struct hwpm_ip th500_hwpm_ip_nvltx;
+
+#else
+#define TH500_HWPM_ACTIVE_IP_NVLTX
+#endif
+
+#endif /* TH500_HWPM_IP_NVLTX_H */

drivers/tegra/hwpm/hal/th500/soc/th500_soc_perfmon_device_index.h

@@ -161,8 +161,8 @@ enum th500_hwpm_soc_perfmon_device_index {
 	TH500_NVLRX9_PERFMON_DEVICE_NODE_INDEX,
 	TH500_NVLRX10_PERFMON_DEVICE_NODE_INDEX,
 	TH500_NVLRX11_PERFMON_DEVICE_NODE_INDEX,
-	TH500_CTRL0_PERFMON_DEVICE_NODE_INDEX,
+	TH500_NVLCTRL0_PERFMON_DEVICE_NODE_INDEX,
-	TH500_CTRL1_PERFMON_DEVICE_NODE_INDEX,
+	TH500_NVLCTRL1_PERFMON_DEVICE_NODE_INDEX,
 	TH500_CTC0_PERFMON_DEVICE_NODE_INDEX,
 	TH500_CTC1_PERFMON_DEVICE_NODE_INDEX,
 	TH500_PMA_DEVICE_NODE_INDEX,

drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c

@@ -147,7 +147,23 @@ struct allowlist th500_rtr_alist[5] = {
 	{0x0000004c, false},
 };
 
-struct allowlist th500_nvlink_alist[0] = {
+struct allowlist th500_nvlrx_alist[5] = {
+	{0x00003340, false},
+	{0x00000d00, false},
+	{0x00000d04, false},
+	{0x00001d00, false},
+	{0x00001d04, false},
+};
+
+struct allowlist th500_nvltx_alist[3] = {
+	{0x00000180, false},
+	{0x00001500, false},
+	{0x00001504, false},
+};
+
+struct allowlist th500_nvlctrl_alist[2] = {
+	{0x00000804, false},
+	{0x00000808, false},
 };
 
 struct allowlist th500_smmu_alist[1] = {

drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h

@@ -25,7 +25,9 @@ extern struct allowlist th500_perfmon_alist[67];
 extern struct allowlist th500_pma_res_cmd_slice_rtr_alist[44];
 extern struct allowlist th500_pma_res_pma_alist[1];
 extern struct allowlist th500_rtr_alist[5];
-extern struct allowlist th500_nvlink_alist[0];
+extern struct allowlist th500_nvlrx_alist[5];
+extern struct allowlist th500_nvltx_alist[3];
+extern struct allowlist th500_nvlctrl_alist[2];
 extern struct allowlist th500_smmu_alist[1];
 extern struct allowlist th500_c2c_alist[52];
 extern struct allowlist th500_pcie_alist[1];

drivers/tegra/hwpm/hal/th500/th500_interface.c

@@ -159,8 +159,14 @@ bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
 		break;
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
-	case TEGRA_HWPM_IP_C_NVLINK:
+	case TEGRA_HWPM_IP_NVLCTRL:
-		config_ip = TH500_HWPM_IP_C_NVLINK;
+		config_ip = TH500_HWPM_IP_NVLCTRL;
+		break;
+	case TEGRA_HWPM_IP_NVLRX:
+		config_ip = TH500_HWPM_IP_NVLRX;
+		break;
+	case TEGRA_HWPM_IP_NVLTX:
+		config_ip = TH500_HWPM_IP_NVLTX;
 		break;
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_PCIE)
@@ -230,8 +236,14 @@ bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
 		break;
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
-	case TEGRA_HWPM_RESOURCE_C_NVLINK:
+	case TEGRA_HWPM_RESOURCE_NVLCTRL:
-		config_ip = TH500_HWPM_IP_C_NVLINK;
+		config_ip = TH500_HWPM_IP_NVLCTRL;
+		break;
+	case TEGRA_HWPM_RESOURCE_NVLRX:
+		config_ip = TH500_HWPM_IP_NVLRX;
+		break;
+	case TEGRA_HWPM_RESOURCE_NVLTX:
+		config_ip = TH500_HWPM_IP_NVLTX;
 		break;
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_PCIE)
@@ -313,7 +325,9 @@ int th500_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm)
 	th500_active_ip_info[TH500_HWPM_IP_SMMU] = &th500_hwpm_ip_smmu;
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
-	th500_active_ip_info[TH500_HWPM_IP_C_NVLINK] = &th500_hwpm_ip_c_nvlink;
+	th500_active_ip_info[TH500_HWPM_IP_NVLCTRL] = &th500_hwpm_ip_nvlctrl;
+	th500_active_ip_info[TH500_HWPM_IP_NVLRX] = &th500_hwpm_ip_nvlrx;
+	th500_active_ip_info[TH500_HWPM_IP_NVLTX] = &th500_hwpm_ip_nvltx;
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_SOC_HUB)
 	th500_active_ip_info[TH500_HWPM_IP_SOC_HUB] = &th500_hwpm_ip_soc_hub;

drivers/tegra/hwpm/hal/th500/th500_internal.h

@@ -29,6 +29,9 @@
 #include <hal/th500/soc/ip/c2c/th500_c2c.h>
 #include <hal/th500/soc/ip/smmu/th500_smmu.h>
 #include <hal/th500/soc/ip/cl2/th500_cl2.h>
+#include <hal/th500/soc/ip/c_nvlink/th500_nvlrx.h>
+#include <hal/th500/soc/ip/c_nvlink/th500_nvltx.h>
+#include <hal/th500/soc/ip/c_nvlink/th500_nvlctrl.h>
 
 #define TH500_HWPM_ACTIVE_IP_MAX		TH500_HWPM_IP_MAX
 
@@ -39,6 +42,9 @@
 	DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_C2C)		\
 	DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_SMMU)		\
 	DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_CL2)		\
+	DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLCTRL)		\
+	DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLRX)   	\
+	DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLTX)   	\
 	DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX)
 
 #undef DEFINE_SOC_HWPM_ACTIVE_IP

drivers/tegra/hwpm/hal/th500/th500_ip.c

@@ -65,7 +65,9 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
 	case TH500_HWPM_IP_SMMU:
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
-	case TH500_HWPM_IP_C_NVLINK:
+	case TH500_HWPM_IP_NVLCTRL:
+	case TH500_HWPM_IP_NVLRX:
+	case TH500_HWPM_IP_NVLTX:
 #endif
 #if defined(CONFIG_TH500_HWPM_IP_PCIE)
 	case TH500_HWPM_IP_PCIE:

drivers/tegra/hwpm/include/tegra_hwpm.h

@@ -80,6 +80,9 @@ enum tegra_hwpm_ip_enum {
 	TEGRA_HWPM_IP_C2C,
 	TEGRA_HWPM_IP_SMMU,
 	TEGRA_HWPM_IP_CL2,
+	TEGRA_HWPM_IP_NVLCTRL,
+	TEGRA_HWPM_IP_NVLRX,
+	TEGRA_HWPM_IP_NVLTX,
 	TERGA_HWPM_NUM_IPS
 };
 
@@ -111,6 +114,9 @@ enum tegra_hwpm_resource_enum {
 	TEGRA_HWPM_RESOURCE_C2C,
 	TEGRA_HWPM_RESOURCE_SMMU,
 	TEGRA_HWPM_RESOURCE_CL2,
+	TEGRA_HWPM_RESOURCE_NVLCTRL,
+	TEGRA_HWPM_RESOURCE_NVLRX,
+	TEGRA_HWPM_RESOURCE_NVLTX,
 	TERGA_HWPM_NUM_RESOURCES
 };
 

drivers/tegra/hwpm/os/linux/ip_utils.c

@@ -96,6 +96,15 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
 	case TEGRA_SOC_HWPM_IP_CL2:
 		ip_enum_idx = TEGRA_HWPM_IP_CL2;
 		break;
+	case TEGRA_SOC_HWPM_IP_NVLCTRL:
+		ip_enum_idx = TEGRA_HWPM_IP_NVLCTRL;
+		break;
+	case TEGRA_SOC_HWPM_IP_NVLRX:
+		ip_enum_idx = TEGRA_HWPM_IP_NVLRX;
+		break;
+	case TEGRA_SOC_HWPM_IP_NVLTX:
+		ip_enum_idx = TEGRA_HWPM_IP_NVLTX;
+		break;
 	default:
 		tegra_hwpm_err(hwpm,
 			"Queried enum tegra_soc_hwpm_ip %d is invalid",
@@ -207,6 +216,15 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
 	case TEGRA_SOC_HWPM_RESOURCE_CL2:
 		res_enum_idx = TEGRA_HWPM_RESOURCE_CL2;
 		break;
+	case TEGRA_SOC_HWPM_RESOURCE_NVLCTRL:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_NVLCTRL;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_NVLRX:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_NVLRX;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_NVLTX:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_NVLTX;
+		break;
 	default:
 		tegra_hwpm_err(hwpm,
 			"Queried enum tegra_soc_hwpm_resource %d is invalid",

include/uapi/linux/tegra-soc-hwpm-uapi.h

@@ -47,6 +47,9 @@ enum tegra_soc_hwpm_ip {
 	TEGRA_SOC_HWPM_IP_C2C,
 	TEGRA_SOC_HWPM_IP_SMMU,
 	TEGRA_SOC_HWPM_IP_CL2,
+	TEGRA_SOC_HWPM_IP_NVLCTRL,
+	TEGRA_SOC_HWPM_IP_NVLRX,
+	TEGRA_SOC_HWPM_IP_NVLTX,
 	TERGA_SOC_HWPM_NUM_IPS
 };
 
@@ -116,6 +119,9 @@ enum tegra_soc_hwpm_resource {
 	TEGRA_SOC_HWPM_RESOURCE_C2C,
 	TEGRA_SOC_HWPM_RESOURCE_SMMU,
 	TEGRA_SOC_HWPM_RESOURCE_CL2,
+	TEGRA_SOC_HWPM_RESOURCE_NVLCTRL,
+	TEGRA_SOC_HWPM_RESOURCE_NVLRX,
+	TEGRA_SOC_HWPM_RESOURCE_NVLTX,
 	TERGA_SOC_HWPM_NUM_RESOURCES
 };