nv-tegra-mirror/linux-hwpm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-hwpm.git synced 2025-12-24 02:07:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

tegra: hwpm: improve common function readability

Browse Source 
- HALs get_rtr_int_idx and get_ip_max_idx return the chip specific
router index and number of IPs. This information is static for a chip
and doesn't require any input. Hence, update the HAL definition to not
require hwpm pointer as an argument. Update definition and references
for these HALs.
- Add new HAL to get PMA and RTR structure pointers. Implement and
update other chip specific functions to use new HAL.
- Add new timer macro to check a condition and timeout after given
retries. Update necessary code to use new timer macro.
- Correct validate_emc_config function to compute correct available mss
channel mask based on fuse value.
- Update tegra_hwpm_readl and tegra_hwpm_writel macros to assert error
value. This way error checks are added at one spot and not sprinkled all
over the driver code.
- Update get_mem_bytes_put_ptr() and membuf_overflow_status() to return
error as function return and accept arguments to return mem_head pointer
and overflow status respectively. Add overflow status macros to use
throughout driver. Update HAL definition and references accordingly.
- conftest is only compiled for OOT config atm. Add OOT config check to
include conftest header.

Jira THWPM-109

Change-Id: I77d150e860fa344a1604d241e27718150fdb8647
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2982555
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Vishal Aslot <vaslot@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2023-09-20 14:18:38 -07:00
committed by mobile promotions
parent bc1f044c15
commit da3bda1364
28 changed files with 534 additions and 953 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/tegra/hwpm/os/linux/mem_mgmt_utils.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -360,7 +360,8 @@ fail:
int tegra_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm,
struct tegra_soc_hwpm_update_get_put *update_get_put)
{
int ret;
int ret = 0;
u32 overflowed_status = 0U;
tegra_hwpm_fn(hwpm, " ");
@@ -382,7 +383,7 @@ int tegra_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm,
update_get_put->mem_bump);
if (ret != 0) {
tegra_hwpm_err(hwpm, "Failed to update mem_bytes get ptr");
return -EINVAL;
return ret;
}
/* Stream MEM_BYTES value to MEM_BYTES buffer */
@@ -396,16 +397,25 @@ int tegra_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm,
/* Read HW put pointer */
if (update_get_put->b_read_mem_head) {
update_get_put->mem_head =
hwpm->active_chip->get_mem_bytes_put_ptr(hwpm);
ret = hwpm->active_chip->get_mem_bytes_put_ptr(hwpm,
&update_get_put->mem_head);
if (ret != 0) {
tegra_hwpm_err(hwpm, "Failed to get mem_bytes put ptr");
return ret;
}
tegra_hwpm_dbg(hwpm, hwpm_dbg_update_get_put,
"MEM_HEAD = 0x%llx", update_get_put->mem_head);
}
/* Check overflow error status */
if (update_get_put->b_check_overflow) {
update_get_put->b_overflowed =
(u8) hwpm->active_chip->membuf_overflow_status(hwpm);
ret = hwpm->active_chip->membuf_overflow_status(hwpm,
&overflowed_status);
if (ret != 0) {
tegra_hwpm_err(hwpm, "Failed to get overflow status");
return ret;
}
update_get_put->b_overflowed = (u8) overflowed_status;
tegra_hwpm_dbg(hwpm, hwpm_dbg_update_get_put, "OVERFLOWED = %u",
update_get_put->b_overflowed);
}