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tegra:hwpm:th500: Force-enablement support for IPs

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This patch adds support to selectively force-enable
TH500 IPs using module parameters.

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: I684169ad52da466b51e6b18634a997563390b0a4
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3026101
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vishal Aslot
2023-12-01 03:31:13 +00:00
committed by mobile promotions
parent 11de2bc045
commit fdbe788448
23 changed files with 335 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -270,7 +270,7 @@ static struct hwpm_ip_aperture th500_c2c_inst1_broadcast_element_static_array[
};
/* IP instance array */
static struct hwpm_ip_inst th500_c2c_inst_static_array[
struct hwpm_ip_inst th500_c2c_inst_static_array[
TH500_HWPM_IP_C2C_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

2
drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

4
drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlctrl.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -112,7 +112,7 @@ static struct hwpm_ip_aperture th500_nvlctrl_inst1_perfmux_element_static_array[
};
/* IP instance array */
static struct hwpm_ip_inst th500_nvlctrl_inst_static_array[
struct hwpm_ip_inst th500_nvlctrl_inst_static_array[
TH500_HWPM_IP_NVLCTRL_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlrx.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -862,7 +862,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_broadcast_element_static_array[
};
/* IP instance array */
static struct hwpm_ip_inst th500_nvlrx_inst_static_array[
struct hwpm_ip_inst th500_nvlrx_inst_static_array[
TH500_HWPM_IP_NVLRX_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvltx.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -862,7 +862,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_broadcast_element_static_array[
};
/* IP instance array */
static struct hwpm_ip_inst th500_nvltx_inst_static_array[
struct hwpm_ip_inst th500_nvltx_inst_static_array[
TH500_HWPM_IP_NVLTX_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -474,7 +474,7 @@ static struct hwpm_ip_aperture th500_cl2_inst7_perfmux_element_static_array[
};
/* IP instance array */
static struct hwpm_ip_inst th500_cl2_inst_static_array[
struct hwpm_ip_inst th500_cl2_inst_static_array[
TH500_HWPM_IP_CL2_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -243,7 +243,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_broadcast_element_static_arra
};
/* IP instance array */
static struct hwpm_ip_inst th500_mcf_c2c_inst_static_array[
struct hwpm_ip_inst th500_mcf_c2c_inst_static_array[
TH500_HWPM_IP_MCF_C2C_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -273,7 +273,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_broadcast_element_static_ar
};
/* IP instance array */
static struct hwpm_ip_inst th500_mcf_clink_inst_static_array[
struct hwpm_ip_inst th500_mcf_clink_inst_static_array[
TH500_HWPM_IP_MCF_CLINK_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -557,7 +557,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_broadcast_element_static_arr
};
/* IP instance array */
static struct hwpm_ip_inst th500_mcf_core_inst_static_array[
struct hwpm_ip_inst th500_mcf_core_inst_static_array[
TH500_HWPM_IP_MCF_CORE_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -92,7 +92,7 @@ static struct hwpm_ip_aperture th500_mcf_iobhx_inst0_broadcast_element_static_ar
};
/* IP instance array */
static struct hwpm_ip_inst th500_mcf_iobhx_inst_static_array[
struct hwpm_ip_inst th500_mcf_iobhx_inst_static_array[
TH500_HWPM_IP_MCF_IOBHX_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -122,7 +122,7 @@ static struct hwpm_ip_aperture th500_mcf_ocu_inst0_broadcast_element_static_arra
};
/* IP instance array */
static struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[
struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[
TH500_HWPM_IP_MCF_OCU_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1053,7 +1053,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_broadcast_element_static_
};
/* IP instance array */
static struct hwpm_ip_inst th500_mss_channel_inst_static_array[
struct hwpm_ip_inst th500_mss_channel_inst_static_array[
TH500_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -309,7 +309,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_broadcast_element_static_arra
};
/* IP instance array */
static struct hwpm_ip_inst th500_mss_hub_inst_static_array[
struct hwpm_ip_inst th500_mss_hub_inst_static_array[
TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -424,7 +424,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst9_perfmux_element_static_arr
};
/* IP instance array */
static struct hwpm_ip_inst th500_pcie_xalrc_inst_static_array[
struct hwpm_ip_inst th500_pcie_xalrc_inst_static_array[
TH500_HWPM_IP_PCIE_XALRC_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -424,7 +424,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst9_perfmux_element_static_arra
};
/* IP instance array */
static struct hwpm_ip_inst th500_pcie_xtlq_inst_static_array[
struct hwpm_ip_inst th500_pcie_xtlq_inst_static_array[
TH500_HWPM_IP_PCIE_XTLQ_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -424,7 +424,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst9_perfmux_element_static_arr
};
/* IP instance array */
static struct hwpm_ip_inst th500_pcie_xtlrc_inst_static_array[
struct hwpm_ip_inst th500_pcie_xtlrc_inst_static_array[
TH500_HWPM_IP_PCIE_XTLRC_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

4
drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -229,7 +229,7 @@ static struct hwpm_ip_aperture th500_smmu_inst4_perfmux_element_static_array[
};
/* IP instance array */
static struct hwpm_ip_inst th500_smmu_inst_static_array[
struct hwpm_ip_inst th500_smmu_inst_static_array[
TH500_HWPM_IP_SMMU_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),

69
drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c
View File

@@ -1,24 +1,29 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* This file is autogenerated. Do not edit.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "th500_soc_regops_allowlist.h"
struct allowlist th500_perfmon_alist[67] = {
struct allowlist th500_perfmon_alist[76] = {
{0x00000000, true},
{0x00000004, true},
{0x00000008, true},
@@ -86,9 +91,18 @@ struct allowlist th500_perfmon_alist[67] = {
{0x00000124, true},
{0x00000128, true},
{0x00000130, true},
{0x0000012c, true},
{0x00000138, true},
{0x00000140, true},
{0x00000148, true},
{0x00000150, true},
{0x00000154, true},
{0x0000015c, true},
{0x00000144, true},
{0x0000014c, true},
};
struct allowlist th500_pma_res_cmd_slice_rtr_alist[44] = {
struct allowlist th500_pma_res_cmd_slice_rtr_alist[56] = {
{0x00000800, false},
{0x00000a00, false},
{0x00000a10, false},
@@ -102,6 +116,9 @@ struct allowlist th500_pma_res_cmd_slice_rtr_alist[44] = {
{0x00000a4c, false},
{0x00000a50, false},
{0x00000a54, false},
{0x00000608, false},
{0x00000a30, false},
{0x00000a34, false},
{0x00000a58, false},
{0x00000a5c, false},
{0x00000ae4, false},
@@ -132,19 +149,41 @@ struct allowlist th500_pma_res_cmd_slice_rtr_alist[44] = {
{0x00000b54, false},
{0x00000b58, false},
{0x00000b5c, false},
{0x00000ae0, false},
{0x00000aec, false},
{0x00000af8, false},
{0x00000b60, false},
{0x0000075c, false},
{0x00000700, false},
{0x00001ffc, false},
{0x00000604, false},
{0x00000600, false},
{0x000009f0, false},
};
struct allowlist th500_pma_res_pma_alist[1] = {
{0x00000800, true},
};
struct allowlist th500_rtr_alist[5] = {
struct allowlist th500_rtr_alist[18] = {
{0x0000001c, false},
{0x0000005c, false},
{0x00000044, false},
{0x00000010, false},
{0x00000050, false},
{0x00000048, false},
{0x00000008, false},
{0x0000004c, false},
{0x00000060, false},
{0x00000064, false},
{0x00000068, false},
{0x0000006c, false},
{0x00000070, false},
{0x00000074, false},
{0x00000078, false},
{0x0000007c, false},
{0x00000080, false},
{0x00000084, false},
};
struct allowlist th500_nvlrx_alist[5] = {

38
drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h
View File

@@ -1,19 +1,24 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* This file is autogenerated. Do not edit.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef TH500_HWPM_REGOPS_ALLOWLIST_H
@@ -21,10 +26,10 @@
#include <tegra_hwpm.h>
extern struct allowlist th500_perfmon_alist[67];
extern struct allowlist th500_pma_res_cmd_slice_rtr_alist[44];
extern struct allowlist th500_perfmon_alist[76];
extern struct allowlist th500_pma_res_cmd_slice_rtr_alist[56];
extern struct allowlist th500_pma_res_pma_alist[1];
extern struct allowlist th500_rtr_alist[5];
extern struct allowlist th500_rtr_alist[18];
extern struct allowlist th500_nvlrx_alist[5];
extern struct allowlist th500_nvltx_alist[3];
extern struct allowlist th500_nvlctrl_alist[2];
@@ -39,8 +44,7 @@ extern struct allowlist th500_mcf_clink_alist[3];
extern struct allowlist th500_mcf_c2c_alist[2];
extern struct allowlist th500_mcf_ocu_alist[1];
extern struct allowlist th500_mcf_iobhx_alist[2];
extern struct allowlist th500_soc_hub_alist[3];
extern struct allowlist th500_cl2_alist[4];
extern struct allowlist th500_mss_hub_alist[3];
extern struct allowlist th500_cl2_alist[4];
#endif /* TH500_HWPM_REGOPS_ALLOWLIST_H */

159
drivers/tegra/hwpm/hal/th500/th500_ip.c
View File

@@ -384,10 +384,11 @@ int th500_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm)
int err;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *chip_ip = NULL;
extern int validate_current_config;
tegra_hwpm_fn(hwpm, " ");
if (!tegra_hwpm_is_platform_silicon()) {
if (!tegra_hwpm_is_platform_silicon() || validate_current_config == 0) {
return 0;
}
@@ -494,39 +495,137 @@ int th500_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm)
int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
{
int ret = 0, err = 0;
#if defined(CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE)
extern int socket_number;
extern long int nvlctrl_mask;
extern long int nvlrx_mask;
extern long int nvltx_mask;
extern long int c2c_mask;
extern long int cl2_mask;
extern long int mcf_c2c_mask;
extern long int mcf_clink_mask;
extern long int mcf_core_mask;
extern long int mcf_iobhx_mask;
extern long int mcf_ocu_mask;
extern long int mss_hub_mask;
extern long int mss_channel_mask;
extern long int pcie_mask;
extern long int smmu_mask;
extern struct hwpm_ip_inst th500_nvlctrl_inst_static_array[];
extern struct hwpm_ip_inst th500_nvlrx_inst_static_array[];
extern struct hwpm_ip_inst th500_nvltx_inst_static_array[];
extern struct hwpm_ip_inst th500_c2c_inst_static_array[];
extern struct hwpm_ip_inst th500_cl2_inst_static_array[];
extern struct hwpm_ip_inst th500_mcf_c2c_inst_static_array[];
extern struct hwpm_ip_inst th500_mcf_clink_inst_static_array[];
extern struct hwpm_ip_inst th500_mcf_core_inst_static_array[];
extern struct hwpm_ip_inst th500_mcf_iobhx_inst_static_array[];
extern struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[];
extern struct hwpm_ip_inst th500_mss_hub_inst_static_array[];
extern struct hwpm_ip_inst th500_mss_channel_inst_static_array[];
extern struct hwpm_ip_inst th500_pcie_xalrc_inst_static_array[];
extern struct hwpm_ip_inst th500_pcie_xtlrc_inst_static_array[];
extern struct hwpm_ip_inst th500_pcie_xtlq_inst_static_array[];
extern struct hwpm_ip_inst th500_smmu_inst_static_array[];
#endif /* CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE */
int err = 0;
#if defined(CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE)
int ret = 0;
int ip, inst;
const u32 socket_shift = 44; /* bits */
u64 socket_offset, base_addr;
struct hwpm_ip_inst *ip_inst = NULL;
struct hwpm_ip_element_info *elem_info = NULL;
struct hwpm_force_enable_ip {
char name[16];
long int mask;
int id;
int instances;
struct hwpm_ip_inst *inst_static_array;
};
struct hwpm_force_enable_ip force_enable_ips[] = {
{"none", 0, 0, 0, NULL},
#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
{"nvlctrl", nvlctrl_mask, TH500_HWPM_IP_NVLCTRL, TH500_HWPM_IP_NVLCTRL_NUM_INSTANCES, th500_nvlctrl_inst_static_array},
{"nvlrx", nvlrx_mask, TH500_HWPM_IP_NVLRX, TH500_HWPM_IP_NVLRX_NUM_INSTANCES, th500_nvlrx_inst_static_array},
{"nvltx", nvltx_mask, TH500_HWPM_IP_NVLTX, TH500_HWPM_IP_NVLTX_NUM_INSTANCES, th500_nvltx_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_C2C)
{"c2c", c2c_mask, TH500_HWPM_IP_C2C, TH500_HWPM_IP_C2C_NUM_INSTANCES, th500_c2c_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_CL2)
{"cl2", cl2_mask, TH500_HWPM_IP_CL2, TH500_HWPM_IP_CL2_NUM_INSTANCES, th500_cl2_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_MCF_C2C)
{"mcf_c2c", mcf_c2c_mask, TH500_HWPM_IP_MCF_C2C, TH500_HWPM_IP_MCF_C2C_NUM_INSTANCES, th500_mcf_c2c_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_MCF_CLINK)
{"mcf_clink", mcf_clink_mask, TH500_HWPM_IP_MCF_CLINK, TH500_HWPM_IP_MCF_CLINK_NUM_INSTANCES, th500_mcf_clink_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_MCF_CORE)
{"mcf_core", mcf_core_mask, TH500_HWPM_IP_MCF_CORE, TH500_HWPM_IP_MCF_CORE_NUM_INSTANCES, th500_mcf_core_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX)
{"mcf_iobhx", mcf_iobhx_mask, TH500_HWPM_IP_MCF_IOBHX, TH500_HWPM_IP_MCF_IOBHX_NUM_INSTANCES, th500_mcf_iobhx_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU)
{"mcf_ocu", mcf_ocu_mask, TH500_HWPM_IP_MCF_OCU, TH500_HWPM_IP_MCF_OCU_NUM_INSTANCES, th500_mcf_ocu_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB)
{"mss_hub", mss_hub_mask, TH500_HWPM_IP_MSS_HUB, TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES, th500_mss_hub_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
{"mss_channel", mss_channel_mask, TH500_HWPM_IP_MSS_CHANNEL, TH500_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES, th500_mss_channel_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
{"pcie_xalrc", pcie_mask, TH500_HWPM_IP_PCIE_XALRC, TH500_HWPM_IP_PCIE_XALRC_NUM_INSTANCES, th500_pcie_xalrc_inst_static_array},
{"pcie_xtlrc", pcie_mask, TH500_HWPM_IP_PCIE_XTLRC, TH500_HWPM_IP_PCIE_XTLRC_NUM_INSTANCES, th500_pcie_xtlrc_inst_static_array},
{"pcie_xtlq", pcie_mask, TH500_HWPM_IP_PCIE_XTLQ, TH500_HWPM_IP_PCIE_XTLQ_NUM_INSTANCES, th500_pcie_xtlq_inst_static_array},
#endif
#if defined(CONFIG_TH500_HWPM_IP_SMMU)
{"smmu", smmu_mask, TH500_HWPM_IP_SMMU, TH500_HWPM_IP_SMMU_NUM_INSTANCES, th500_smmu_inst_static_array},
#endif
};
int force_enable_ips_size = sizeof(force_enable_ips)/sizeof(force_enable_ips[0]);
#endif /* CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE */
tegra_hwpm_fn(hwpm, " ");
#if defined(CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE)
/* MSS CHANNEL */
#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_mc0_base_r(), TH500_HWPM_IP_MSS_CHANNEL, true);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"TH500_HWPM_IP_MSS_CHANNEL force enable failed");
err = ret;
}
#endif
#if defined(CONFIG_TH500_HWPM_IP_C2C)
/* CTC Link */
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_c2c0_base_r(), TH500_HWPM_IP_C2C, true);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"TH500_HWPM_IP_C2C force enable failed");
return ret;
}
socket_offset = (u64)socket_number << socket_shift;
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_c2c5_base_r(), TH500_HWPM_IP_C2C, true);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"TH500_HWPM_IP_C2C force enable failed");
return ret;
for (ip = 1; ip < force_enable_ips_size; ip++) {
struct hwpm_force_enable_ip *current_ip = &force_enable_ips[ip];
tegra_hwpm_err(hwpm, "Force enabling %s on socket %d", current_ip->name,
socket_number);
for (inst = 0; inst < current_ip->instances; inst++) {
if (!(current_ip->mask & (1ULL << inst))) {
continue;
}
tegra_hwpm_err(hwpm, "\tenabling instance %d...", inst);
ip_inst = &current_ip->inst_static_array[inst];
elem_info = &ip_inst->element_info[TEGRA_HWPM_APERTURE_TYPE_PERFMUX];
base_addr = socket_offset + elem_info->range_start;
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
base_addr, current_ip->id, true);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"%s force enable failed for instance %d",
current_ip->name, inst);
err = ret;
}
}
}
#endif
#endif
#endif /* CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE */
return err;
}
}

10
drivers/tegra/hwpm/include/tegra_hwpm_log.h
View File

@@ -78,6 +78,16 @@ enum tegra_soc_hwpm_log_type {
/* Active debug prints */
#define hwpm_dbg_active BIT(18)
/* All debug bits */
#define hwpm_dbg_all_bits \
(hwpm_info | hwpm_fn | hwpm_register | hwpm_verbose | \
hwpm_dbg_driver_init | hwpm_dbg_ip_register | hwpm_dbg_device_info | \
hwpm_dbg_floorsweep_info | hwpm_dbg_resource_info | \
hwpm_dbg_reserve_resource | hwpm_dbg_release_resource | \
hwpm_dbg_alloc_pma_stream | hwpm_dbg_bind | hwpm_dbg_allowlist | \
hwpm_dbg_regops | hwpm_dbg_update_get_put | hwpm_dbg_driver_release | \
hwpm_dbg_kmem)
#ifdef __KERNEL__
#define tegra_hwpm_err(hwpm, fmt, arg...) \

5
drivers/tegra/hwpm/os/linux/debugfs.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -25,6 +25,7 @@
void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux)
{
struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
extern int dbg_mask;
if (!hwpm_linux) {
tegra_hwpm_err(hwpm, "Invalid hwpm_linux struct");
@@ -42,6 +43,8 @@ void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux)
debugfs_create_u32("log_mask", S_IRUGO|S_IWUSR,
hwpm_linux->debugfs_root, &hwpm->dbg_mask);
hwpm->dbg_mask = ((u32)dbg_mask & hwpm_dbg_all_bits);
return;
fail:

84
drivers/tegra/hwpm/os/linux/driver.c
View File

@@ -19,11 +19,13 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/moduleparam.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/dma-buf.h>
#include <linux/debugfs.h>
#include <linux/stat.h>
#include <tegra_hwpm.h>
#include <tegra_hwpm_ip.h>
@@ -36,6 +38,68 @@
#include <os/linux/driver.h>
#include <os/linux/acpi.h>
/*
* Optional module parameters
*/
#define S_IRWUG (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP)
/* Debug mask at driver load time. Can be overridden via debugfs later */
int dbg_mask = 0;
module_param(dbg_mask, int, S_IRWUG);
/* This is a WAR on TH500 */
int validate_current_config = 1;
module_param(validate_current_config, int, S_IRWUG);
/*
* IP software masks to be used for force-enablement.
* 0x0 means "do not force-enable"
*/
long int nvlctrl_mask = 0x0;
module_param(nvlctrl_mask, long, S_IRWUG);
long int nvlrx_mask = 0x0;
module_param(nvlrx_mask, long, S_IRWUG);
long int nvltx_mask = 0x0;
module_param(nvltx_mask, long, S_IRWUG);
long int c2c_mask = 0x0;
module_param(c2c_mask, long, S_IRWUG);
long int cl2_mask = 0x0;
module_param(cl2_mask, long, S_IRWUG);
long int mcf_c2c_mask = 0x0;
module_param(mcf_c2c_mask, long, S_IRWUG);
long int mcf_clink_mask = 0x0;
module_param(mcf_clink_mask, long, S_IRWUG);
long int mcf_core_mask = 0x0;
module_param(mcf_core_mask, long, S_IRWUG);
long int mcf_iobhx_mask = 0x0;
module_param(mcf_iobhx_mask, long, S_IRWUG);
long int mcf_ocu_mask = 0x0;
module_param(mcf_ocu_mask, long, S_IRWUG);
long int mss_channel_mask = 0x0;
module_param(mss_channel_mask, long, S_IRWUG);
long int mss_hub_mask = 0x0;
module_param(mss_hub_mask, long, S_IRWUG);
long int pcie_mask = 0x0;
module_param(pcie_mask, long, S_IRWUG);
long int smmu_mask = 0x0;
module_param(smmu_mask, long, S_IRWUG);
/* Socket number */
int socket_number = 0x0;
static const struct of_device_id tegra_soc_hwpm_of_match[] = {
{
.compatible = "nvidia,t234-soc-hwpm",
@@ -53,6 +117,26 @@ static const struct of_device_id tegra_soc_hwpm_of_match[] = {
};
MODULE_DEVICE_TABLE(of, tegra_soc_hwpm_of_match);
/*
* The socket number must be 0, 1, 2, or 3.
*/
static int set_socket_number(const char *val, const struct kernel_param *kp)
{
int socket_num = 0, ret;
ret = kstrtoint(val, 10, &socket_num);
if (ret != 0 || socket_num < 0 || socket_num > 3)
return -EINVAL;
return param_set_int(val, kp);
}
static const struct kernel_param_ops param_ops = {
.set = set_socket_number,
.get = param_get_int,
};
module_param_cb(socket, &param_ops, &socket_number, S_IRWUG | S_IROTH);
#if defined(NV_CLASS_STRUCT_DEVNODE_HAS_CONST_DEV_ARG)
static char *tegra_hwpm_get_devnode(const struct device *dev, umode_t *mode)
#else