Commit Graph

5 Commits

Author SHA1 Message Date
Vishal Aslot
2f26b5849e tegra: hwpm: th500: Add support for MCF SOC
This patch adds support for MCF SOC performance
monitoring in the driver. MCF SOC has two different
types of perfmuxes connected to the same perfmon:
one is the OCU type and the other is IBHX and OBHX.
IBHX is only accessible via MC16 aperture. Therefore,
this patch adds two separate IPs: OCU and IOBHX.
However, both are tied to the MCF SOC perfmon (mcfsoc0).

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: If15498a44e02270f9106337078931edbe043c254
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2986232
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
2023-11-07 22:42:42 -08:00
Vishal Aslot
b689a36372 tegra: hwpm: th500: Add support for MSS HUB
This patch adds support for MSS HUB performance
monitoring in the driver.

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: I35b8c8c9bf1eb8b43dc1baeb10a9701fbd3f2dd9
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2987019
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
2023-11-07 02:33:43 -08:00
Vishal Aslot
bc6fdf1f18 tegra: hwpm: th500: Add support for C-NVLINK
This patch adds support for C-NVLINK performance
monitoring in the driver. C-NVLINK consists of
RX, TX, and CTRL apertures, each with its own
perfmux signals and perfmons. So this patch
breaks them up into three sets of perfmux-perfmon
data structures.

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: Id8be4c965018125765f75a7b8bc8ab809bb7f976
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2999166
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
2023-11-07 02:33:34 -08:00
Vedashree Vidwans
da3bda1364 tegra: hwpm: improve common function readability
- HALs get_rtr_int_idx and get_ip_max_idx return the chip specific
router index and number of IPs. This information is static for a chip
and doesn't require any input. Hence, update the HAL definition to not
require hwpm pointer as an argument. Update definition and references
for these HALs.
- Add new HAL to get PMA and RTR structure pointers. Implement and
update other chip specific functions to use new HAL.
- Add new timer macro to check a condition and timeout after given
retries. Update necessary code to use new timer macro.
- Correct validate_emc_config function to compute correct available mss
channel mask based on fuse value.
- Update tegra_hwpm_readl and tegra_hwpm_writel macros to assert error
value. This way error checks are added at one spot and not sprinkled all
over the driver code.
- Update get_mem_bytes_put_ptr() and membuf_overflow_status() to return
error as function return and accept arguments to return mem_head pointer
and overflow status respectively. Add overflow status macros to use
throughout driver. Update HAL definition and references accordingly.
- conftest is only compiled for OOT config atm. Add OOT config check to
include conftest header.

Jira THWPM-109

Change-Id: I77d150e860fa344a1604d241e27718150fdb8647
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2982555
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Vishal Aslot <vaslot@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-10-05 04:30:46 -07:00
Vishal Aslot
c630042921 tegra: hwpm: th500: Merge hwpm-th500 files in hwpm
This patch carefully merges approved TH500 files from kernel/hwpm-next
into this public repo.

Bug 4266701

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: Ia869b75e1652c214e32c53f0edb3d4bf709d72f4
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2972033
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-09-21 21:16:39 -07:00