Enum tegra_soc_hwpm_ip is defined to query IP information. To untangle
its use from HWPM related functionality, enum tegra_soc_hwpm_resource
should be used by IP drivers to register with HWPM.
An IP can have multiple instances with multiple IP core elements in
each instance. Currently, the IP <-> HWPM register access API passes
register offset only. However, it is not possible to figure out
requested specific register access only with register offset. For
example, MC device has one instance with 16 duplicate channels. To
access channel x perfmux register, HWPM driver should pass perfmux
register offset alongwith channel number (index).
Add instance element index as an argument to the register access API,
tegra_soc_hwpm_ip_ops.hwpm_ip_reg_op().
-Update internal copy of tegra_soc_hwpm_ip_ops.
-Update hwpm_ip_reg_op() implemented in flcn driver.
-Update hwpm_ip_reg_op() implemented in pva driver.
Update hwpm_ip_pm() in flcn driver to use nvhost power management APIs.
Bug 3573882
Jira THWPM-8
Change-Id: I0138927f383e9a67085816132ce33538bd609560
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2713274
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
- Many HWPM functions are performed on all apertures of all instances of
all IPs. Define below resource utility functions to perform a task on
all IPs, instances and apertures:
- tegra_hwpm_func_all_IPs
- tegra_hwpm_func_single_ip
- tegra_hwpm_func_all_instance
- tegra_hwpm_func_single_instance
- tegra_hwpm_func_all_perfmuxes
- tegra_hwpm_func_all_perfmons
- tegra_hwpm_func_single_aperture
- Modify below functions to use above mentioned utility functions:
- get allowlist size
- combine allowlist
- reserve resources
- bind resources
- release resources
This will make code more legible and maintainable.
This patch also defines new function that validates all HAL
initializations for the chip.
Jira THWPM-41
Change-Id: Icaeba4d94187b97022c0a6626584e7d61ab6d0e4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2705524
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add below HALs to make code chip agnostic. This will allow us to use
t234 specific HALs for next chips.
- get_pma_int_idx: get PMA's internal index corresponding to active chip
- get_rtr_int_idx: get RTR's internal index corresponding to active chip
- get_ip_max_idx: get MAX IP index corresponding to active chip
Move chip agnostic code to common files.
Jira THWPM-41
Change-Id: I5518469b1473fe7f66b6517cee729cf46520bbac
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675515
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
HWPM supports various IPs which initialize at different times in boot
flow. Some IPs such as MSS, NVLINK initialize before HWPM device and
some IPs (VIC, OFA, NVDEC, NVDLA) are initialized after HWPM device.
Modify IP register function to store registration requests in a
linked list for IPs initialized before HWPM device is probed.
The linked list will be traversed to complete pending IP register
requests after HWPM device is initialized.
- Add struct tegra_hwpm_ip_ops internal to HWPM driver to include only
required ip_ops details.
- Replace init_fs_info HAL with finalize_chip_info to register ip_ops,
force enable IPs (if any).
Jira THWPM-41
Change-Id: I916b4fa50679e79025a941a9c1fc113bdfe92b41
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675472
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
- Update HWPM driver to add HAL layer. This will allow support for multiple chips.
- Add below data structure hierarchy for HWPM driver
HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array
NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon"
- Chip info structure contains
- Array of IP info
- HAL function pointers
- IP info structure contains IP specific info
- Number of instances
- Number of apertures per instance
- Aperture ranges, strides, static info array
- Aperture dynamic arrays
- Aperture info structure contains
- Hw index
- Physical address info
- MMIO address info
- Add separate IP info files
- Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible.
- Move probe, ioctl and io functions to os/linux path.
- Add fn, info, register and verbose debug log levels to controls debug messages
- add debugfs node to update dbg_mask
- Correct MGBE perfmux base address
Jira THWPM-41
Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
