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tegra: hwpm: update floorsweep info IOCTL

Browse Source 
- Update tegra_soc_hwpm_ip enum to hold only IPs which can be
floorswept.
- Update floorsweep_info IOCTL to return floorsweepable component
details of tegra_soc_hwpm_ip IPs.

Bug 3573882

Change-Id: Ia62222ba8afdf60b25d0f3701bfd2be215bb6071
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2713363
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2022-05-16 13:16:50 -07:00
committed by mobile promotions
parent dd86a4afb2
commit 6fa5d10ca0
41 changed files with 191 additions and 107 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
common/tegra_hwpm_ip_utils.c
View File

@@ -20,6 +20,33 @@
#include <tegra_hwpm_common.h>
#include <tegra_hwpm_static_analysis.h>
int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
{
int ret = 0;
u32 i = 0U;
tegra_hwpm_fn(hwpm, " ");
for (i = 0U; i < fs_info->num_queries; i++) {
ret = hwpm->active_chip->get_fs_info(
hwpm, (u32)fs_info->ip_fsinfo[i].ip,
&fs_info->ip_fsinfo[i].ip_inst_mask,
&fs_info->ip_fsinfo[i].status);
if (ret < 0) {
/* Print error for debug purpose. */
tegra_hwpm_err(hwpm, "Failed to get fs_info");
}
tegra_hwpm_dbg(hwpm, hwpm_verbose,
"Query %d: ip %d: ip_status: %d inst_mask 0x%llx",
i, fs_info->ip_fsinfo[i].ip,
fs_info->ip_fsinfo[i].status,
fs_info->ip_fsinfo[i].ip_inst_mask);
}
return ret;
}
int tegra_hwpm_get_resource_info(struct tegra_soc_hwpm *hwpm,
struct tegra_soc_hwpm_resource_info *rsrc_info)
{

2
hal/t234/ip/display/t234_hwpm_ip_display.c
View File

@@ -60,6 +60,8 @@ struct hwpm_ip_inst t234_display_inst_static_array[
T234_HWPM_IP_DISPLAY_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_DISPLAY_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

1
hal/t234/ip/display/t234_hwpm_ip_display.h
View File

@@ -19,6 +19,7 @@
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_DISPLAY_NUM_INSTANCES 1U
#define T234_HWPM_IP_DISPLAY_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_BROADCAST_PER_INST 0U

2
hal/t234/ip/isp/t234_hwpm_ip_isp.c
View File

@@ -60,6 +60,8 @@ struct hwpm_ip_inst t234_isp_inst_static_array[
T234_HWPM_IP_ISP_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

11
hal/t234/ip/isp/t234_hwpm_ip_isp.h
View File

@@ -15,13 +15,14 @@
#define T234_HWPM_IP_ISP_H
#if defined(CONFIG_SOC_HWPM_IP_ISP)
#define T234_HWPM_ACTIVE_IP_ISP T234_HWPM_IP_ISP
#define T234_HWPM_ACTIVE_IP_ISP T234_HWPM_IP_ISP
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_ISP_NUM_INSTANCES 1U
#define T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_ISP_NUM_INSTANCES 1U
#define T234_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_isp;

8
hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.c
View File

@@ -174,6 +174,8 @@ struct hwpm_ip_inst t234_mgbe_inst_static_array[
T234_HWPM_IP_MGBE_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_MGBE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -233,6 +235,8 @@ struct hwpm_ip_inst t234_mgbe_inst_static_array[
},
{
.hw_inst_mask = BIT(1),
.num_core_elements_per_inst =
T234_HWPM_IP_MGBE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -292,6 +296,8 @@ struct hwpm_ip_inst t234_mgbe_inst_static_array[
},
{
.hw_inst_mask = BIT(2),
.num_core_elements_per_inst =
T234_HWPM_IP_MGBE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -351,6 +357,8 @@ struct hwpm_ip_inst t234_mgbe_inst_static_array[
},
{
.hw_inst_mask = BIT(3),
.num_core_elements_per_inst =
T234_HWPM_IP_MGBE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

1
hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.h
View File

@@ -19,6 +19,7 @@
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MGBE_NUM_INSTANCES 4U
#define T234_HWPM_IP_MGBE_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST 0U

2
hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.c
View File

@@ -528,6 +528,8 @@ struct hwpm_ip_inst t234_mss_channel_inst_static_array[
T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_MSS_CHANNEL T234_HWPM_IP_MSS_CHANNEL
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST 1U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST 1U
extern struct hwpm_ip t234_hwpm_ip_mss_channel;

2
hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.c
View File

@@ -165,6 +165,8 @@ struct hwpm_ip_inst t234_mss_gpu_hub_inst_static_array[
T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_MSS_GPU_HUB_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_MSS_GPU_HUB T234_HWPM_IP_MSS_GPU_HUB
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST 8U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_CORE_ELEMENT_PER_INST 8U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST 8U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_mss_gpu_hub;

2
hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.c
View File

@@ -222,6 +222,8 @@ struct hwpm_ip_inst t234_mss_iso_niso_hub_inst_static_array[
T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_MSS_ISO_NISO_HUBS T234_HWPM_IP_MSS_ISO_NISO_HUBS
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST 2U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST 9U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST 1U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_CORE_ELEMENT_PER_INST 9U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST 2U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST 9U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST 1U
extern struct hwpm_ip t234_hwpm_ip_mss_iso_niso_hubs;

2
hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.c
View File

@@ -214,6 +214,8 @@ struct hwpm_ip_inst t234_mss_mcf_inst_static_array[
T234_HWPM_IP_MSS_MCF_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_MSS_MCF_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

1
hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.h
View File

@@ -19,6 +19,7 @@
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_MCF_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_MCF_NUM_CORE_ELEMENT_PER_INST 8U
#define T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST 3U
#define T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST 8U
#define T234_HWPM_IP_MSS_MCF_NUM_BROADCAST_PER_INST 1U

2
hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.c
View File

@@ -60,6 +60,8 @@ struct hwpm_ip_inst t234_nvdec_inst_static_array[
T234_HWPM_IP_NVDEC_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_NVDEC_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

1
hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.h
View File

@@ -19,6 +19,7 @@
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_NVDEC_NUM_INSTANCES 1U
#define T234_HWPM_IP_NVDEC_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_BROADCAST_PER_INST 0U

4
hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.c
View File

@@ -98,6 +98,8 @@ struct hwpm_ip_inst t234_nvdla_inst_static_array[
T234_HWPM_IP_NVDLA_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_NVDLA_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -157,6 +159,8 @@ struct hwpm_ip_inst t234_nvdla_inst_static_array[
},
{
.hw_inst_mask = BIT(1),
.num_core_elements_per_inst =
T234_HWPM_IP_NVDLA_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

1
hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.h
View File

@@ -19,6 +19,7 @@
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_NVDLA_NUM_INSTANCES 2U
#define T234_HWPM_IP_NVDLA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_BROADCAST_PER_INST 0U

2
hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.c
View File

@@ -60,6 +60,8 @@ struct hwpm_ip_inst t234_nvenc_inst_static_array[
T234_HWPM_IP_NVENC_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_NVENC_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

1
hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.h
View File

@@ -19,6 +19,7 @@
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_NVENC_NUM_INSTANCES 1U
#define T234_HWPM_IP_NVENC_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_NVENC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_NVENC_NUM_BROADCAST_PER_INST 0U

2
hal/t234/ip/ofa/t234_hwpm_ip_ofa.c
View File

@@ -60,6 +60,8 @@ struct hwpm_ip_inst t234_ofa_inst_static_array[
T234_HWPM_IP_OFA_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_OFA_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/ofa/t234_hwpm_ip_ofa.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_OFA T234_HWPM_IP_OFA
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_OFA_NUM_INSTANCES 1U
#define T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_OFA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_OFA_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_OFA_NUM_INSTANCES 1U
#define T234_HWPM_IP_OFA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_OFA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_OFA_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_ofa;

22
hal/t234/ip/pcie/t234_hwpm_ip_pcie.c
View File

@@ -440,6 +440,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
T234_HWPM_IP_PCIE_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -499,6 +501,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(1),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -558,6 +562,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(2),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -617,6 +623,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(3),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -676,6 +684,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(4),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -735,6 +745,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(5),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -794,6 +806,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(6),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -853,6 +867,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(7),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -912,6 +928,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(8),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -971,6 +989,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(9),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -1030,6 +1050,8 @@ struct hwpm_ip_inst t234_pcie_inst_static_array[
},
{
.hw_inst_mask = BIT(10),
.num_core_elements_per_inst =
T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

1
hal/t234/ip/pcie/t234_hwpm_ip_pcie.h
View File

@@ -19,6 +19,7 @@
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_PCIE_NUM_INSTANCES 11U
#define T234_HWPM_IP_PCIE_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST 0U

2
hal/t234/ip/pma/t234_hwpm_ip_pma.c
View File

@@ -60,6 +60,8 @@ struct hwpm_ip_inst t234_pma_inst_static_array[
T234_HWPM_IP_PMA_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_PMA_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/pma/t234_hwpm_ip_pma.h
View File

@@ -17,10 +17,11 @@
#define T234_HWPM_ACTIVE_IP_PMA T234_HWPM_IP_PMA
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_PMA_NUM_INSTANCES 1U
#define T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_PMA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_PMA_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_PMA_NUM_INSTANCES 1U
#define T234_HWPM_IP_PMA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_PMA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_PMA_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_pma;

2
hal/t234/ip/pva/t234_hwpm_ip_pva.c
View File

@@ -90,6 +90,8 @@ struct hwpm_ip_inst t234_pva_inst_static_array[
T234_HWPM_IP_PVA_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_PVA_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/pva/t234_hwpm_ip_pva.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_PVA T234_HWPM_IP_PVA
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_PVA_NUM_INSTANCES 1U
#define T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST 3U
#define T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_PVA_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_PVA_NUM_INSTANCES 1U
#define T234_HWPM_IP_PVA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST 3U
#define T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_PVA_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_pva;

4
hal/t234/ip/rtr/t234_hwpm_ip_rtr.c
View File

@@ -63,6 +63,8 @@ struct hwpm_ip_inst t234_rtr_inst_static_array[
T234_HWPM_IP_RTR_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_RTR_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -120,6 +122,8 @@ struct hwpm_ip_inst t234_rtr_inst_static_array[
},
{
.hw_inst_mask = BIT(1),
.num_core_elements_per_inst =
T234_HWPM_IP_RTR_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

15
hal/t234/ip/rtr/t234_hwpm_ip_rtr.h
View File

@@ -17,14 +17,15 @@
#define T234_HWPM_ACTIVE_IP_RTR T234_HWPM_IP_RTR
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_RTR_NUM_INSTANCES 2U
#define T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST 0U
#define T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_RTR_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_RTR_NUM_INSTANCES 2U
#define T234_HWPM_IP_RTR_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST 0U
#define T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_RTR_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_RTR_STATIC_RTR_INST 0U
#define T234_HWPM_IP_RTR_STATIC_PMA_INST 1U
#define T234_HWPM_IP_RTR_PERMUX_INDEX 0U
#define T234_HWPM_IP_RTR_STATIC_RTR_INST 0U
#define T234_HWPM_IP_RTR_STATIC_PMA_INST 1U
#define T234_HWPM_IP_RTR_PERMUX_INDEX 0U
extern struct hwpm_ip t234_hwpm_ip_rtr;

2
hal/t234/ip/scf/t234_hwpm_ip_scf.c
View File

@@ -41,6 +41,8 @@ struct hwpm_ip_inst t234_scf_inst_static_array[
T234_HWPM_IP_SCF_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_SCF_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/scf/t234_hwpm_ip_scf.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_SCF T234_HWPM_IP_SCF
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_SCF_NUM_INSTANCES 1U
#define T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_SCF_NUM_PERFMUX_PER_INST 0U
#define T234_HWPM_IP_SCF_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_SCF_NUM_INSTANCES 1U
#define T234_HWPM_IP_SCF_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_SCF_NUM_PERFMUX_PER_INST 0U
#define T234_HWPM_IP_SCF_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_scf;

4
hal/t234/ip/vi/t234_hwpm_ip_vi.c
View File

@@ -98,6 +98,8 @@ struct hwpm_ip_inst t234_vi_inst_static_array[
T234_HWPM_IP_VI_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_VI_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
@@ -158,6 +160,8 @@ struct hwpm_ip_inst t234_vi_inst_static_array[
},
{
.hw_inst_mask = BIT(1),
.num_core_elements_per_inst =
T234_HWPM_IP_VI_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/vi/t234_hwpm_ip_vi.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_VI T234_HWPM_IP_VI
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_VI_NUM_INSTANCES 2U
#define T234_HWPM_IP_VI_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_VI_NUM_INSTANCES 2U
#define T234_HWPM_IP_VI_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_vi;

2
hal/t234/ip/vic/t234_hwpm_ip_vic.c
View File

@@ -60,6 +60,8 @@ struct hwpm_ip_inst t234_vic_inst_static_array[
T234_HWPM_IP_VIC_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T234_HWPM_IP_VIC_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to

9
hal/t234/ip/vic/t234_hwpm_ip_vic.h
View File

@@ -18,10 +18,11 @@
#define T234_HWPM_ACTIVE_IP_VIC T234_HWPM_IP_VIC
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_VIC_NUM_INSTANCES 1U
#define T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_VIC_NUM_INSTANCES 1U
#define T234_HWPM_IP_VIC_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_vic;

8
hal/t234/t234_hwpm_interface_utils.c
View File

@@ -221,11 +221,11 @@ static bool t234_hwpm_validate_hals(struct tegra_soc_hwpm *hwpm)
}
bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
u32 ip_index, u32 *config_ip_index)
u32 ip_enum, u32 *config_ip_index)
{
u32 config_ip = TEGRA_SOC_HWPM_IP_INACTIVE;
switch (ip_index) {
switch (ip_enum) {
case TEGRA_SOC_HWPM_IP_VI:
#if defined(CONFIG_SOC_HWPM_IP_VI)
config_ip = T234_HWPM_IP_VI;
@@ -307,8 +307,8 @@ bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
#endif
break;
default:
tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_ip %d invalid",
ip_index);
tegra_hwpm_err(hwpm,
"Queried enum tegra_soc_hwpm_ip %d invalid", ip_enum);
break;
}

45
hal/t234/t234_hwpm_ip_utils.c
View File

@@ -152,10 +152,7 @@ fail:
int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
{
u32 i = 0U;
int ret = 0;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *chip_ip = NULL;
tegra_hwpm_fn(hwpm, " ");
@@ -300,13 +297,6 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
}
}
tegra_hwpm_dbg(hwpm, hwpm_verbose, "IP floorsweep info:");
for (i = 0U; i < active_chip->get_ip_max_idx(hwpm); i++) {
chip_ip = active_chip->chip_ips[i];
tegra_hwpm_dbg(hwpm, hwpm_verbose, "IP:%d fs_mask:0x%x",
i, chip_ip->inst_fs_mask);
}
fail:
return ret;
}
@@ -314,41 +304,40 @@ fail:
int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
u32 ip_enum, u64 *fs_mask, u8 *ip_status)
{
u32 ip_idx = 0U;
u32 ip_idx = 0U, inst_idx = 0U, element_mask_shift = 0U;
u64 floorsweep = 0ULL;
struct tegra_soc_hwpm_chip *active_chip = NULL;
struct hwpm_ip *chip_ip = NULL;
struct hwpm_ip_inst *ip_inst = NULL;
tegra_hwpm_fn(hwpm, " ");
/* Convert tegra_soc_hwpm_ip to internal enum */
/* Convert tegra_soc_hwpm_ip enum to internal ip index */
if (!(t234_hwpm_is_ip_active(hwpm, ip_enum, &ip_idx))) {
tegra_hwpm_dbg(hwpm, hwpm_info,
"SOC hwpm IP %d is not configured", ip_enum);
"SOC hwpm IP %d is unavailable", ip_enum);
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_INVALID;
*fs_mask = 0ULL;
/* Remove after uapi update */
if (ip_enum == TEGRA_SOC_HWPM_IP_MSS_NVLINK) {
tegra_hwpm_dbg(hwpm, hwpm_verbose,
"For hwpm IP %d setting status as valid",
ip_enum);
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID;
}
return 0;
}
active_chip = hwpm->active_chip;
chip_ip = active_chip->chip_ips[ip_idx];
ip_inst = &chip_ip->ip_inst_static_array[0U];
/* TODO: Update after fS IOCTL discussion */
if (ip_idx == T234_HWPM_IP_MSS_CHANNEL) {
*fs_mask = ip_inst->element_fs_mask;
} else {
*fs_mask = chip_ip->inst_fs_mask;
}
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID;
for (inst_idx = 0U; inst_idx < chip_ip->num_instances; inst_idx++) {
ip_inst = &chip_ip->ip_inst_static_array[inst_idx];
element_mask_shift = (inst_idx == 0U ?
0U : ip_inst->num_core_elements_per_inst);
if (ip_inst->hw_inst_mask & chip_ip->inst_fs_mask) {
floorsweep = (floorsweep << element_mask_shift);
floorsweep |= ((u64)ip_inst->element_fs_mask);
}
}
*fs_mask = floorsweep;
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID;
return 0;
}

9
include/tegra_hwpm.h
View File

@@ -223,6 +223,15 @@ struct hwpm_ip_inst {
*/
u32 hw_inst_mask;
/*
* An IP instance is a group of core elements of the IP
* Eg., channels in MSS, controllers in PCIe
* Performance tracking is counted by 0, 1 or more HWPM components
* (perfmux/perfmon) connected to each IP core element.
*
*/
u32 num_core_elements_per_inst;
/* Element details specific to this instance */
struct hwpm_ip_element_info element_info[TEGRA_HWPM_APERTURE_TYPE_MAX];

27
os/linux/tegra_hwpm_ip.c
View File

@@ -145,30 +145,3 @@ void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
}
}
}
int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
{
int ret = 0;
u32 i = 0U;
tegra_hwpm_fn(hwpm, " ");
for (i = 0U; i < fs_info->num_queries; i++) {
ret = hwpm->active_chip->get_fs_info(
hwpm, (u32)fs_info->ip_fsinfo[i].ip_type,
&fs_info->ip_fsinfo[i].ip_inst_mask,
&fs_info->ip_fsinfo[i].status);
if (ret < 0) {
/* Print error for debug purpose. */
tegra_hwpm_err(hwpm, "Failed to get fs_info");
}
tegra_hwpm_dbg(hwpm, hwpm_verbose,
"Query %d: ip_type %d: ip_status: %d inst_mask 0x%llx",
i, fs_info->ip_fsinfo[i].ip_type,
fs_info->ip_fsinfo[i].status,
fs_info->ip_fsinfo[i].ip_inst_mask);
}
return ret;
}