mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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6fa5d10ca0
- Update tegra_soc_hwpm_ip enum to hold only IPs which can be floorswept. - Update floorsweep_info IOCTL to return floorsweepable component details of tegra_soc_hwpm_ip IPs. Bug 3573882 Change-Id: Ia62222ba8afdf60b25d0f3701bfd2be215bb6071 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2713363 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
171 lines
4.4 KiB
C
171 lines
4.4 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "t234_hwpm_ip_isp.h"
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_hwpm_regops_allowlist.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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struct hwpm_ip_aperture t234_isp_inst0_perfmon_element_static_array[
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T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST] = {
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{
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.element_type = HWPM_ELEMENT_PERFMON,
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.element_index_mask = BIT(0),
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.dt_index = 0U,
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.dt_mmio = NULL,
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.name = "perfmon_isp0",
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.start_abs_pa = addr_map_rpg_pm_isp0_base_r(),
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.end_abs_pa = addr_map_rpg_pm_isp0_limit_r(),
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.start_pa = 0,
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.end_pa = 0,
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.base_pa = addr_map_rpg_pm_base_r(),
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.alist = t234_perfmon_alist,
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.alist_size = ARRAY_SIZE(t234_perfmon_alist),
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.fake_registers = NULL,
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},
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};
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struct hwpm_ip_aperture t234_isp_inst0_perfmux_element_static_array[
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T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST] = {
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{
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.element_type = IP_ELEMENT_PERFMUX,
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.element_index_mask = BIT(0),
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.dt_index = 0U,
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.dt_mmio = NULL,
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.name = {'\0'},
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.start_abs_pa = addr_map_isp_thi_base_r(),
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.end_abs_pa = addr_map_isp_thi_limit_r(),
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.start_pa = 0,
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.end_pa = 0,
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.base_pa = 0ULL,
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.alist = t234_isp_thi_alist,
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.alist_size = ARRAY_SIZE(t234_isp_thi_alist),
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.fake_registers = NULL,
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},
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};
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/* IP instance array */
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struct hwpm_ip_inst t234_isp_inst_static_array[
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T234_HWPM_IP_ISP_NUM_INSTANCES] = {
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{
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.hw_inst_mask = BIT(0),
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.num_core_elements_per_inst =
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T234_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST,
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.element_info = {
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/*
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* Instance info corresponding to
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* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
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*/
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{
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.num_element_per_inst =
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T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST,
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.element_static_array =
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t234_isp_inst0_perfmux_element_static_array,
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.range_start = addr_map_isp_thi_base_r(),
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.range_end = addr_map_isp_thi_limit_r(),
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.element_stride = addr_map_isp_thi_limit_r() -
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addr_map_isp_thi_base_r() + 1ULL,
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.element_slots = 0U,
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.element_arr = NULL,
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},
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/*
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* Instance info corresponding to
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* TEGRA_HWPM_APERTURE_TYPE_BROADCAST
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*/
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{
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.num_element_per_inst =
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T234_HWPM_IP_ISP_NUM_BROADCAST_PER_INST,
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.element_static_array = NULL,
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.range_start = 0ULL,
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.range_end = 0ULL,
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.element_stride = 0ULL,
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.element_slots = 0U,
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.element_arr = NULL,
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},
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/*
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* Instance info corresponding to
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* TEGRA_HWPM_APERTURE_TYPE_PERFMON
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*/
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{
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.num_element_per_inst =
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T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST,
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.element_static_array =
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t234_isp_inst0_perfmon_element_static_array,
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.range_start = addr_map_rpg_pm_isp0_base_r(),
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.range_end = addr_map_rpg_pm_isp0_limit_r(),
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.element_stride = addr_map_rpg_pm_isp0_limit_r() -
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addr_map_rpg_pm_isp0_base_r() + 1ULL,
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.element_slots = 0U,
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.element_arr = NULL,
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},
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},
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.ip_ops = {
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.ip_dev = NULL,
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.hwpm_ip_pm = NULL,
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.hwpm_ip_reg_op = NULL,
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},
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.element_fs_mask = 0U,
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},
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};
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struct hwpm_ip t234_hwpm_ip_isp = {
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.num_instances = T234_HWPM_IP_ISP_NUM_INSTANCES,
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.ip_inst_static_array = t234_isp_inst_static_array,
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.inst_aperture_info = {
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/*
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* Instance info corresponding to
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* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
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*/
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{
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.range_start = addr_map_isp_thi_base_r(),
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.range_end = addr_map_isp_thi_limit_r(),
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.inst_stride = addr_map_isp_thi_limit_r() -
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addr_map_isp_thi_base_r() + 1ULL,
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.inst_slots = 0U,
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.inst_arr = NULL,
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},
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/*
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* Instance info corresponding to
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* TEGRA_HWPM_APERTURE_TYPE_BROADCAST
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*/
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{
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.range_start = 0ULL,
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.range_end = 0ULL,
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.inst_stride = 0ULL,
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.inst_slots = 0U,
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.inst_arr = NULL,
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},
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/*
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* Instance info corresponding to
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* TEGRA_HWPM_APERTURE_TYPE_PERFMON
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*/
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{
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.range_start = addr_map_rpg_pm_isp0_base_r(),
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.range_end = addr_map_rpg_pm_isp0_limit_r(),
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.inst_stride = addr_map_rpg_pm_isp0_limit_r() -
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addr_map_rpg_pm_isp0_base_r() + 1ULL,
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.inst_slots = 0U,
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.inst_arr = NULL,
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},
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},
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.override_enable = false,
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.inst_fs_mask = 0U,
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.resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID,
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.reserved = false,
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};
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