Add below HALs to make code chip agnostic. This will allow us to use
t234 specific HALs for next chips.
- get_pma_int_idx: get PMA's internal index corresponding to active chip
- get_rtr_int_idx: get RTR's internal index corresponding to active chip
- get_ip_max_idx: get MAX IP index corresponding to active chip
Move chip agnostic code to common files.
Jira THWPM-41
Change-Id: I5518469b1473fe7f66b6517cee729cf46520bbac
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675515
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
HWPM supports various IPs which initialize at different times in boot
flow. Some IPs such as MSS, NVLINK initialize before HWPM device and
some IPs (VIC, OFA, NVDEC, NVDLA) are initialized after HWPM device.
Modify IP register function to store registration requests in a
linked list for IPs initialized before HWPM device is probed.
The linked list will be traversed to complete pending IP register
requests after HWPM device is initialized.
- Add struct tegra_hwpm_ip_ops internal to HWPM driver to include only
required ip_ops details.
- Replace init_fs_info HAL with finalize_chip_info to register ip_ops,
force enable IPs (if any).
Jira THWPM-41
Change-Id: I916b4fa50679e79025a941a9c1fc113bdfe92b41
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675472
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Set the floorsweeping information for IPs only
if the configuration is non Hypervisor. Force
enable IPs are only valid for native-Linux config.
On hypervisor config, a driver is allowed to only
remap addresses owned by the device node.
Thus, ioremap of perfmux addresses is not allowed
in hypervisor configuration. Add check to prevent
force enable IPs and ioremap in hypervisor
configuration.
JIRA THWPM-45
Change-Id: I8fe6d3c4984c66be5a117e0cc2164ea20a5374cb
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2674003
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
For MSS channel, hwpm client expects floorsweep info mask to indicate
available MSS chanenel perfmuxes.
HWPM driver would prefer to follow common fs_mask logic for IPs and is
being discussed.
Temporarily update floorsweep info logic for MSS channel, until
floorsweep info IOCTL modifications are finalized.
Bug 3477617
Change-Id: I75b51ccc60151e801dec50fa32b15b951db6e47e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2672291
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
- Update HWPM driver to add HAL layer. This will allow support for multiple chips.
- Add below data structure hierarchy for HWPM driver
HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array
NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon"
- Chip info structure contains
- Array of IP info
- HAL function pointers
- IP info structure contains IP specific info
- Number of instances
- Number of apertures per instance
- Aperture ranges, strides, static info array
- Aperture dynamic arrays
- Aperture info structure contains
- Hw index
- Physical address info
- MMIO address info
- Add separate IP info files
- Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible.
- Move probe, ioctl and io functions to os/linux path.
- Add fn, info, register and verbose debug log levels to controls debug messages
- add debugfs node to update dbg_mask
- Correct MGBE perfmux base address
Jira THWPM-41
Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Move chip specific code to chip specific folder. This will allow
multiple chip support in the future.
Create new specific functions
- Initialize hwpm structures
- Reserve and release PMA and RTR apertures
- Zero, update and check allowlists
- Set and get fake registers for MC aperture on simulation
- perfmon dt aperture enums
Jira THWPM-41
Change-Id: Ib80f324283c8d29b5c6f7bb6345a6df2410954e6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2620234
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
