tegra: hwpm: Fix EMC Fuse Mask calculation.

A recent change has led to EMC fuse mask calculation regression.
This is being corrected in this patch. The emc_fuse_disable mask is
set in such a way that, each bit corresponds to 4 MSS Channels.
For example, emc_fuse_disable mask=1100, corresponds to MSS_Channel0
to MSS_Channel7 being present, while MSS_Channel8 to MSS_Channel15
are floorswept. However, in HWPM Driver, the logic to represent
a floorswept IP element is indicated by '1'. Correct the logic to
indicate this.

Bug 5247662

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: Ia3825db29715e04aa43822283b160252d00f0a81
(cherry picked from commit 89426a7e0a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3358321
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Yifei Wan <ywan@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com>

drivers/tegra/hwpm/hal/t234/t234_ip.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MIT
 /*
- * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -212,6 +212,7 @@ static int t234_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm)
 	u32 emc_disable_fuse_val = 0U;
 	u32 emc_disable_fuse_val_mask = 0xFU;
 	u32 emc_element_floorsweep_mask = 0U;
+	u32 emc_disable_fuse_bit_idx = 0U;
 	u32 idx = 0U;
 	int err;
 
@@ -235,11 +236,11 @@ static int t234_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm)
 	 * Convert floorsweep fuse value to available EMC elements.
 	 */
 	do {
-		if (emc_disable_fuse_val & 0x1U) {
-			emc_element_floorsweep_mask =
-				(emc_element_floorsweep_mask << 4U) | 0xFU;
+		if (!(emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx))) {
+			emc_element_floorsweep_mask |=
+				(0xFU << (emc_disable_fuse_bit_idx * 4U));
 		}
-		emc_disable_fuse_val = (emc_disable_fuse_val >> 1U);
+		emc_disable_fuse_bit_idx++;
 		emc_disable_fuse_val_mask = (emc_disable_fuse_val_mask >> 1U);
 	} while (emc_disable_fuse_val_mask != 0U);
 

drivers/tegra/hwpm/os/linux/driver.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,6 +14,8 @@
  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <nvidia/conftest.h>
+
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/module.h>
@@ -21,7 +23,6 @@
 #include <linux/slab.h>
 #include <linux/dma-buf.h>
 #include <linux/debugfs.h>
-#include <linux/version.h>
 
 #include <tegra_hwpm.h>
 #include <tegra_hwpm_ip.h>
@@ -50,10 +51,10 @@ static const struct of_device_id tegra_soc_hwpm_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, tegra_soc_hwpm_of_match);
 
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
-static char *tegra_hwpm_get_devnode(struct device *dev, umode_t *mode)
-#else
+#if defined(NV_CLASS_STRUCT_DEVNODE_HAS_CONST_DEV_ARG)
 static char *tegra_hwpm_get_devnode(const struct device *dev, umode_t *mode)
+#else
+static char *tegra_hwpm_get_devnode(struct device *dev, umode_t *mode)
 #endif
 {
 	if (!mode) {
@@ -110,7 +111,6 @@ static int tegra_hwpm_probe(struct platform_device *pdev)
 	hwpm_linux->pdev = pdev;
 	hwpm_linux->dev = &pdev->dev;
 	hwpm_linux->np = pdev->dev.of_node;
-	hwpm_linux->class.owner = THIS_MODULE;
 	hwpm_linux->class.name = TEGRA_SOC_HWPM_MODULE_NAME;
 
 	hwpm = &hwpm_linux->hwpm;
@@ -251,9 +251,21 @@ static int tegra_hwpm_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#if defined(NV_PLATFORM_DRIVER_STRUCT_REMOVE_RETURNS_VOID) /* Linux v6.11 */
+static inline void tegra_hwpm_remove_wrapper(struct platform_device *pdev)
+{
+	tegra_hwpm_remove(pdev);
+}
+#else
+static inline int tegra_hwpm_remove_wrapper(struct platform_device *pdev)
+{
+	return tegra_hwpm_remove(pdev);
+}
+#endif
+
 static struct platform_driver tegra_soc_hwpm_pdrv = {
 	.probe		= tegra_hwpm_probe,
-	.remove		= tegra_hwpm_remove,
+	.remove		= tegra_hwpm_remove_wrapper,
 	.driver		= {
 		.name	= TEGRA_SOC_HWPM_MODULE_NAME,
 		.of_match_table = of_match_ptr(tegra_soc_hwpm_of_match),

drivers/tegra/hwpm/os/linux/mem_mgmt_utils.c

@@ -457,8 +457,13 @@ int tegra_hwpm_map_update_allowlist(struct tegra_soc_hwpm *hwpm,
 		goto fail;
 	}
 
+#if defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS) /* Linux v6.5 */
+	pinned_pages = get_user_pages(user_va & PAGE_MASK,
+		hwpm->alist_map->num_pages, 0, hwpm->alist_map->pages);
+#else
 	pinned_pages = get_user_pages(user_va & PAGE_MASK,
 		hwpm->alist_map->num_pages, 0, hwpm->alist_map->pages, NULL);
+#endif
 	if (pinned_pages != hwpm->alist_map->num_pages) {
 		tegra_hwpm_err(hwpm, "Requested %llu pages / Got %ld pages",
 			hwpm->alist_map->num_pages, pinned_pages);