mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 17:30:40 +03:00
9adf6a080d
- Update common function names to tegra_hwpm_* instead of tegra_soc_hwpm_*. - Update header guards to follow similar naming guidelines. Jira THWPM-41 Change-Id: If5ca4f136f5cb6659a99bae42030817142bd242c Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675469 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> GVS: Gerrit_Virtual_Submit
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <soc/tegra/fuse.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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struct platform_device *tegra_soc_hwpm_pdev;
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#define REGISTER_IP true
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#define UNREGISTER_IP false
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void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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int ret = 0;
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if (tegra_soc_hwpm_pdev == NULL) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"IP %d trying to register. HWPM device not available",
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hwpm_ip_ops->ip_index);
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} else {
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if (hwpm_ip_ops->ip_dev == NULL) {
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tegra_hwpm_err(hwpm, "IP dev to register is NULL");
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return;
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}
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"Register IP 0x%llx", hwpm_ip_ops->ip_base_address);
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if (hwpm->active_chip->extract_ip_ops == NULL) {
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tegra_hwpm_err(hwpm, "extract_ip_ops uninitialized");
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return;
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}
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ret = hwpm->active_chip->extract_ip_ops(hwpm,
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hwpm_ip_ops, REGISTER_IP);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "Failed to set IP ops for IP %d",
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hwpm_ip_ops->ip_index);
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}
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}
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}
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void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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int ret = 0;
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if (tegra_soc_hwpm_pdev == NULL) {
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tegra_hwpm_dbg(hwpm, hwpm_info, "HWPM device not available");
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} else {
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if (hwpm_ip_ops->ip_dev == NULL) {
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tegra_hwpm_err(hwpm, "IP dev to unregister is NULL");
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return;
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}
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"Unregister IP 0x%llx", hwpm_ip_ops->ip_base_address);
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if (hwpm->active_chip->extract_ip_ops == NULL) {
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tegra_hwpm_err(hwpm, "extract_ip_ops uninitialized");
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return;
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}
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ret = hwpm->active_chip->extract_ip_ops(hwpm,
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hwpm_ip_ops, UNREGISTER_IP);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "Failed to reset IP ops for IP %d",
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hwpm_ip_ops->ip_index);
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}
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}
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}
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int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
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{
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int ret = 0;
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u32 i = 0U;
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tegra_hwpm_fn(hwpm, " ");
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if (hwpm->active_chip->get_fs_info == NULL) {
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tegra_hwpm_err(hwpm, "get_fs_info uninitialized");
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return -ENODEV;
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}
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for (i = 0U; i < fs_info->num_queries; i++) {
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ret = hwpm->active_chip->get_fs_info(
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hwpm, (u32)fs_info->ip_fsinfo[i].ip_type,
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&fs_info->ip_fsinfo[i].ip_inst_mask,
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&fs_info->ip_fsinfo[i].status);
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if (ret < 0) {
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/* Print error for debug purpose. */
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tegra_hwpm_err(hwpm, "Failed to get fs_info");
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}
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tegra_hwpm_dbg(hwpm, hwpm_verbose,
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"Query %d: ip_type %d: ip_status: %d inst_mask 0x%llx",
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i, fs_info->ip_fsinfo[i].ip_type,
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fs_info->ip_fsinfo[i].status,
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fs_info->ip_fsinfo[i].ip_inst_mask);
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}
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return ret;
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}
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