mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 17:30:40 +03:00
10cd01aa1a
- Some of the APIs are not available on stable kernel. Use kstable specific APIs with LINUX_KERNEL macro condition. - Temporarily comment functions that are not available on Kstable. - Next chip headers are renamed to accommodate more than one next chip. Update next chip includes in init.c and driver.c files. - Rename TEGRA_SOC_HWPM_IP_INACTIVE to TEGRA_HWPM_IP_INACTIVE to follow other macro/enum naming convention. - Use is_resource_active() HAL instead of chip specific function. - Create clock reset functions that will allow us to handle change in APIs on kstable. Jira THWPM-41 Change-Id: I55f58fa51cf9ae96ee9a9565942e68b3b2bb76ee Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2764840 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
138 lines
3.0 KiB
C
138 lines
3.0 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/of.h>
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#include <soc/tegra/fuse-helper.h>
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_soc.h>
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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#if defined(CONFIG_TEGRA_NEXT1_HWPM)
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#include <os/linux/next1_soc_utils.h>
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#endif
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#endif
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u32 tegra_hwpm_get_chip_id_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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if (of_machine_is_compatible("nvidia,tegra234")) {
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return 0x23U;
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}
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#ifdef CONFIG_TEGRA_NEXT1_HWPM
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return tegra_hwpm_next1_get_chip_id_impl();
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#else
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return 0x0U;
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#endif /* CONFIG_TEGRA_NEXT1_HWPM */
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#else
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return (u32)tegra_get_chip_id();
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#endif /* CONFIG_TEGRA_HWPM_OOT */
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}
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u32 tegra_hwpm_get_major_rev_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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if (of_machine_is_compatible("nvidia,tegra234")) {
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return 0x4U;
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}
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#ifdef CONFIG_TEGRA_NEXT1_HWPM
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return tegra_hwpm_next1_get_major_rev_impl();
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#else
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return 0x0U;
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#endif /* CONFIG_TEGRA_NEXT1_HWPM */
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#else
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return (u32)tegra_get_major_rev();
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#endif
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}
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u32 tegra_hwpm_chip_get_revision_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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return 0x0U;
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#else
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return (u32)tegra_chip_get_revision();
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#endif
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}
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u32 tegra_hwpm_get_platform_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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if (of_machine_is_compatible("nvidia,tegra234")) {
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return PLAT_SI;
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}
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#ifdef CONFIG_TEGRA_NEXT1_HWPM
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return tegra_hwpm_next1_get_platform_impl();
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#else
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return PLAT_INVALID;
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#endif /* CONFIG_TEGRA_NEXT1_HWPM */
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#else
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return (u32)tegra_get_platform();
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#endif
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}
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bool tegra_hwpm_is_platform_silicon_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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return tegra_platform_is_silicon();
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#else
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return tegra_platform_is_silicon();
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#endif
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}
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bool tegra_hwpm_is_platform_simulation_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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return tegra_hwpm_get_platform() == PLAT_PRE_SI_VDK;
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#else
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return tegra_platform_is_vdk();
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#endif
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}
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bool tegra_hwpm_is_platform_vsp_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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return tegra_hwpm_get_platform() == PLAT_PRE_SI_VSP;
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#else
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return tegra_platform_is_vsp();
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#endif
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}
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bool tegra_hwpm_is_hypervisor_mode_impl(void)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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return false;
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#else
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return is_tegra_hypervisor_mode();
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#endif
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}
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int tegra_hwpm_fuse_readl_impl(struct tegra_soc_hwpm *hwpm,
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u64 reg_offset, u32 *val)
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{
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u32 fuse_val = 0U;
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int err = 0;
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err = tegra_fuse_readl(reg_offset, &fuse_val);
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if (err != 0) {
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return err;
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}
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*val = fuse_val;
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return 0;
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}
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int tegra_hwpm_fuse_readl_prod_mode_impl(struct tegra_soc_hwpm *hwpm, u32 *val)
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{
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return tegra_hwpm_fuse_readl(hwpm, TEGRA_FUSE_PRODUCTION_MODE, val);
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}
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