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git://nv-tegra.nvidia.com/linux-hwpm.git
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70941decf9
Add a driver for programming the Tegra SOC HWPM path. SOC HWPM allows performance monitoring of various Tegra IPs. The profiling tests cases are configured through IOCTLs sent by a userspace profiling app. The IOCTLs provide the following features: - IP discovery and reservation - Buffer management - Whitelist query - Register read/write ops Bug 200702306 Bug 3305495 Change-Id: I65003b126e01bd03d856767c55aa2424bcfd11fb Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2515148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
137 lines
4.1 KiB
C
137 lines
4.1 KiB
C
/*
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* tegra-soc-hwpm-io.h:
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* This header defines register read/write APIs for the Tegra SOC HWPM driver.
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*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TEGRA_SOC_HWPM_IO_H
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#define TEGRA_SOC_HWPM_IO_H
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#include "tegra-soc-hwpm.h"
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/* Mask and shift field_val so it can be written to a register */
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#define HWPM_REG_F(field, field_val) \
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(((field_val) << field##_SHIFT) & field##_MASK)
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/* Extract a field's value from a register */
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#define HWPM_REG_V(field, reg_val) \
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(((reg_val) & field##_MASK) >> field##_SHIFT)
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/*
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* Check if field_val is set in reg_val. field_val is already masked and
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* shifted to the correct location.
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*/
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#define HWPM_REG_CHECK(reg_val, field_mask, field_val) \
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(((reg_val) & (field_mask)) == ((field_val) & (field_mask)))
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/* Mask and shift field_val. Then check if field_val is set in reg_val. */
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#define HWPM_REG_CHECK_F(reg_val, field, field_val) \
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(((reg_val) & field##_MASK) == HWPM_REG_F(field, (field_val)))
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struct whitelist {
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u64 reg;
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bool zero_in_init;
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};
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struct hwpm_resource_aperture {
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/*
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* If false, this is a HWPM aperture (PERFRMON, PMA or RTR). Else this
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* is a non-HWPM aperture (ex: VIC).
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*/
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bool is_ip;
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/*
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* If is_ip == false, specify dt_aperture for readl/writel operations.
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* If is_ip == true, dt_aperture == TEGRA_SOC_HWPM_INVALID_DT.
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*/
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enum tegra_soc_hwpm_dt_aperture dt_aperture;
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/* Physical aperture */
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u64 start_pa;
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u64 end_pa;
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/* Whitelist */
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struct whitelist *wlist;
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u64 wlist_size;
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/* Fake registers for VDK which doesn't have a SOC HWPM fmodel */
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u32 *fake_registers;
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};
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struct hwpm_resource {
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bool reserved;
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u32 map_size;
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struct hwpm_resource_aperture *map;
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};
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/* Externs */
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extern struct hwpm_resource hwpm_resources[TERGA_SOC_HWPM_NUM_RESOURCES];
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extern u32 *pma_fake_regs;
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extern u32 *mc_fake_regs[16];
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extern struct hwpm_resource_aperture mss_channel_map[];
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extern struct hwpm_resource_aperture mss_iso_niso_hub_map[];
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extern struct hwpm_resource_aperture mss_mcf_map[];
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extern struct hwpm_resource_aperture pma_map[];
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extern struct hwpm_resource_aperture cmd_slice_rtr_map[];
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struct hwpm_resource_aperture *find_hwpm_aperture(struct tegra_soc_hwpm *hwpm,
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u64 phys_addr,
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bool check_reservation);
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u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_dt_aperture dt_aperture,
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u32 reg);
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void hwpm_writel(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_dt_aperture dt_aperture,
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u32 reg,
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u32 val);
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u32 ip_readl(struct tegra_soc_hwpm *hwpm, u64 phys_addr);
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void ip_writel(struct tegra_soc_hwpm *hwpm, u64 phys_addr, u32 val);
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u32 ioctl_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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u64 addr);
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void ioctl_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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u64 addr,
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u32 val);
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int reg_rmw(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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enum tegra_soc_hwpm_dt_aperture dt_aperture,
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u64 addr,
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u32 field_mask,
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u32 field_val,
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bool is_ioctl,
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bool is_ip);
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#define DRIVER_REG_RMW(hwpm, dt_aperture, reg, field, field_val, is_ip) \
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reg_rmw(hwpm, \
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NULL, \
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dt_aperture, \
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reg, \
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field##_MASK, \
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HWPM_REG_F(field, field_val), \
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false, \
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is_ip)
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#define IOCTL_REG_RMW(hwpm, aperture, addr, field_mask, field_val) \
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reg_rmw(hwpm, \
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aperture, \
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aperture->dt_aperture, \
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addr, \
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field_mask, \
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field_val, \
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true, \
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aperture->is_ip)
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#endif /* TEGRA_SOC_HWPM_IO_H */
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