mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 17:30:40 +03:00
913f1b0697
- Zeroing of PMA trigger registers is unnecessary. Remove corresponding logic from HWPM teardown function. - During device open, add a check for PMA/RTR status. This will ensure that PMA/RTR are ready to start new profiling session. Device open will fail if RTR and PMA enginestatus is not ready(idle). - SOC HWPM driver disables and releases all reserved IPs before teardown steps. Update teardown logic to zero out IP allowlist registers during teardown. Jira THWPM-41 Bug 3714516 Change-Id: Iede5a5ed9860e2a73c8e4a04aeedfc061458c793 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2776229 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797444
127 lines
3.0 KiB
C
127 lines
3.0 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_common.h>
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#include <tegra_hwpm_static_analysis.h>
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int tegra_hwpm_perfmux_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmux)
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{
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tegra_hwpm_fn(hwpm, " ");
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return 0;
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}
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int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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tegra_hwpm_fn(hwpm, " ");
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err = tegra_hwpm_func_single_ip(hwpm, NULL,
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TEGRA_HWPM_RESERVE_GIVEN_RESOURCE,
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active_chip->get_rtr_int_idx(hwpm));
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if (err != 0) {
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tegra_hwpm_err(hwpm, "failed to reserve IP %d",
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active_chip->get_rtr_int_idx(hwpm));
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return err;
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}
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return err;
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}
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int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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tegra_hwpm_fn(hwpm, " ");
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err = tegra_hwpm_func_single_ip(hwpm, NULL,
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TEGRA_HWPM_RELEASE_ROUTER,
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active_chip->get_rtr_int_idx(hwpm));
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if (err != 0) {
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tegra_hwpm_err(hwpm, "failed to release IP %d",
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active_chip->get_rtr_int_idx(hwpm));
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return err;
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}
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return err;
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}
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int tegra_hwpm_reserve_resource(struct tegra_soc_hwpm *hwpm, u32 resource)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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u32 ip_idx = TEGRA_HWPM_IP_INACTIVE;
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"User requesting to reserve resource %d", resource);
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/* Translate resource to ip_idx */
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if (!active_chip->is_resource_active(hwpm, resource, &ip_idx)) {
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tegra_hwpm_err(hwpm, "Requested resource %d is unavailable",
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resource);
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return -EINVAL;
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}
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err = tegra_hwpm_func_single_ip(hwpm, NULL,
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TEGRA_HWPM_RESERVE_GIVEN_RESOURCE, ip_idx);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "failed to reserve IP %d", ip_idx);
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return err;
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}
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return 0;
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}
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int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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err = tegra_hwpm_func_all_ip(hwpm, NULL, TEGRA_HWPM_BIND_RESOURCES);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "failed to bind resources");
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return err;
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}
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return err;
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}
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int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm)
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{
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int ret = 0;
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tegra_hwpm_fn(hwpm, " ");
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ret = tegra_hwpm_func_all_ip(hwpm, NULL, TEGRA_HWPM_UNBIND_RESOURCES);
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if (ret != 0) {
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tegra_hwpm_err(hwpm, "failed to release resources");
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return ret;
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}
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ret = tegra_hwpm_func_all_ip(hwpm, NULL, TEGRA_HWPM_RELEASE_RESOURCES);
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if (ret != 0) {
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tegra_hwpm_err(hwpm, "failed to release resources");
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return ret;
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}
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return 0;
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}
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