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scsi: ufs: Clean-up ufs driver

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Done below changes:
1. Removed FPGA specific changes
2. Removed T194 specific changes.
3. Fixed issues reported by check-patch

Change-Id: I8ea07a57add151ccd2e2fdac4e3bd9d9456cc765
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3274557
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Mallikarjun Kasoju
2024-12-27 10:25:22 +00:00
committed by Jon Hunter
parent 76c28404c5
commit 0587b30451
2 changed files with 392 additions and 995 deletions
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691
drivers/scsi/ufs/ufs-tegra-common.c
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File diff suppressed because it is too large Load Diff

178
drivers/scsi/ufs/ufs-tegra.h
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@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only
*/
// Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#ifndef _UFS_TEGRA_H
#define _UFS_TEGRA_H
@@ -15,7 +14,6 @@
#define NV_ADDRESS_MAP_MPHY_L1_BASE 0x02480000
#define NV_ADDRESS_MAP_T23X_UFSHC_VIRT_BASE 0x02520000
#define MPHY_ADDR_RANGE_T234 0x2268
#define MPHY_ADDR_RANGE 0x200
#define UFS_AUX_ADDR_VIRT_RANGE_23X 0x14f
#define NV_ADDRESS_MAP_MPHY_L0_BASE_T264 0xa80b910000
@@ -26,17 +24,11 @@
/* UFS AUX address range in T264 */
#define UFS_AUX_ADDR_RANGE_264 0x100
/* UFS VIRTUALIZATION address for T264 */
#define NV_ADDRESS_MAP_T264_UFSHC_VIRT_BASE 0xa80b8f0000
/* UFS VIRTUALIZATION range in T264 */
#define UFS_AUX_ADDR_VIRT_RANGE_264 0x200
/* UFS AUX Base address for T194 */
#define NV_ADDRESS_MAP_UFSHC_AUX_BASE 0x02460000
/* UFS AUX address range in T194 */
#define UFS_AUX_ADDR_RANGE 0x1C
/* UFS AUX Base address for T234 */
#define NV_ADDRESS_MAP_T23X_UFSHC_AUX_BASE 0x02510000
/* UFS AUX address range in T234 */
@@ -80,10 +72,10 @@
#define MPHY_TX_APB_TX_CLK_CTRL0_0_T234 0x1160
#define MPHY_TX_APB_TX_CLK_CTRL2_0_T234 0x1168
#define MPHY_TX_CLK_EN_SYMB (1 << 1)
#define MPHY_TX_CLK_EN_SLOW (1 << 3)
#define MPHY_TX_CLK_EN_FIXED (1 << 4)
#define MPHY_TX_CLK_EN_3X (1 << 5)
#define MPHY_TX_CLK_EN_SYMB BIT(1)
#define MPHY_TX_CLK_EN_SLOW BIT(3)
#define MPHY_TX_CLK_EN_FIXED BIT(4)
#define MPHY_TX_CLK_EN_3X BIT(5)
#define MPHY_TX_APB_TX_ATTRIBUTE_34_37_0 0x34
#define TX_ADVANCED_GRANULARITY (0x8 << 16)
@@ -114,18 +106,17 @@
#define RX_ADVANCED_MIN_ACTIVATETIME(x) (((x) & 0xf) << 16)
#define RX_ADVANCED_MIN_AT 0xa
#define MPHY_RX_APB_VENDOR2_0 0x184
#define MPHY_RX_APB_VENDOR2_0_T234 0x2184
#define MPHY_RX_APB_VENDOR3_0 0x188
#define MPHY_RX_APB_VENDOR3_0_T234 0x2188
#define MPHY_RX_APB_VENDOR2_0_RX_CAL_EN (1 << 15)
#define MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE (1 << 19)
#define MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL (1 << 26)
#define MPHY_RX_APB_VENDOR2_0_RX_CAL_EN BIT(15)
#define MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE BIT(19)
#define MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL BIT(26)
#define MPHY_TX_APB_TX_VENDOR2_0_T264 0x1108
#define MPHY_TX_APB_VENDOR2_0_TX_CAL_EN (1 << 15)
#define MPHY_TX_APB_VENDOR2_0_TX_CAL_DONE (1 << 19)
#define MPHY_TX_APB_VENDOR2_0_TX_CAL_EN BIT(15)
#define MPHY_TX_APB_VENDOR2_0_TX_CAL_DONE BIT(19)
#define MPHY_RX_CAPABILITY_88_8B_VAL_FPGA 0x4f00fa1a
#define MPHY_RX_CAPABILITY_8C_8F_VAL_FPGA 0x50e080e
@@ -186,32 +177,29 @@ enum ufs_state {
#define UFS_VNDR_HCLKDIV_1US_TICK_T264 0xD0
#define UFS_VNDR_HCLKDIV_1US_TICK_FPGA 0x1A
/*UFS host controller vendor specific registers */
enum {
REG_UFS_VNDR_HCLKDIV = 0xFC,
};
/*
* UFS AUX Registers
*/
#define UFSHC_AUX_UFSHC_STATUS_0 0x10
#define UFSHC_HIBERNATE_STATUS (1 << 0)
#define UFSHC_HIBERNATE_STATUS BIT(0)
#define UFSHC_AUX_UFSHC_DEV_CTRL_0 0x14
#define UFSHC_DEV_CLK_EN (1 << 0)
#define UFSHC_DEV_RESET (1 << 1)
#define UFSHC_DEV_CLK_EN BIT(0)
#define UFSHC_DEV_RESET BIT(1)
#define UFSHC_AUX_UFSHC_SW_EN_CLK_SLCG_0 0x08
#define UFSHC_CLK_OVR_ON (1 << 0)
#define UFSHC_HCLK_OVR_ON (1 << 1)
#define UFSHC_LP_CLK_T_CLK_OVR_ON (1 << 2)
#define UFSHC_CLK_T_CLK_OVR_ON (1 << 3)
#define UFSHC_CG_SYS_CLK_OVR_ON (1 << 4)
#define UFSHC_TX_SYMBOL_CLK_OVR_ON (1 << 5)
#define UFSHC_RX_SYMBOLCLKSELECTED_CLK_OVR_ON (1 << 6)
#define UFSHC_PCLK_OVR_ON (1 << 7)
#define UFSHC_CLK_OVR_ON BIT(0)
#define UFSHC_HCLK_OVR_ON BIT(1)
#define UFSHC_LP_CLK_T_CLK_OVR_ON BIT(2)
#define UFSHC_CLK_T_CLK_OVR_ON BIT(3)
#define UFSHC_CG_SYS_CLK_OVR_ON BIT(4)
#define UFSHC_TX_SYMBOL_CLK_OVR_ON BIT(5)
#define UFSHC_RX_SYMBOLCLKSELECTED_CLK_OVR_ON BIT(6)
#define UFSHC_PCLK_OVR_ON BIT(7)
#define PA_SCRAMBLING 0x1585
#define PA_PEERSCRAMBLING 0x155B
@@ -229,114 +217,6 @@ enum {
#define DME_TC0REPLAYTIMEOUTVAL 0xD042
#define DME_AFC0REQTIMEOUTVAL 0xD043
/*
* MPHY Context save armphy_rx_apb registers
*/
static u16 __attribute__ ((unused)) mphy_rx_apb[] = {
0x080, /* MPHY_RX_APB_CAPABILITY_80_83_0 */
0x084, /* MPHY_RX_APB_CAPABILITY_84_87_0 */
0x088, /* MPHY_RX_APB_CAPABILITY_88_8B_0 */
0x08c, /* MPHY_RX_APB_CAPABILITY_8C_8F_0 */
0x090, /* MPHY_RX_APB_CAPABILITY_90_93_0 */
0x094, /* MPHY_RX_APB_CAPABILITY_94_97_0 */
0x098, /* MPHY_RX_APB_CAPABILITY_98_9B_0 */
0x0a0, /* MPHY_RX_APB_ATTRIBUTE_A0_A3_0 */
0x0a4, /* MPHY_RX_APB_ATTRIBUTE_A4_A7_0 */
0x0a8, /* MPHY_RX_APB_ATTRIBUTE_A8_AB_0 */
0x0d0, /* MPHY_RX_APB_MC_STATUS_D0_D3_0 */
0x0d4, /* MPHY_RX_APB_MC_STATUS_D4_D7_0 */
0x0d8, /* MPHY_RX_APB_MC_STATUS_D8_DB_0 */
0x0dc, /* MPHY_RX_APB_MC_STATUS_DC_DF_0 */
0x0e0, /* MPHY_RX_APB_MC_STATUS_E0_E3_0 */
0x0e4, /* MPHY_RX_APB_MC_STATUS_E4_E7_0 */
0x180, /* MPHY_RX_APB_VENDOR1_0 */
0x184, /* MPHY_RX_APB_VENDOR2_0 */
0x188, /* MPHY_RX_APB_VENDOR3_0 */
0x18c, /* MPHY_RX_APB_VENDOR4_0 */
0x190, /* MPHY_RX_APB_VENDOR5_0 */
0x194, /* MPHY_RX_APB_VENDOR6_0 */
0x198, /* MPHY_RX_APB_VENDOR7_0 */
0x19c, /* MPHY_RX_APB_VENDOR8_0 */
0x1a0, /* MPHY_RX_APB_VENDOR9_0 */
0x1a4, /* MPHY_RX_APB_VENDOR10_0 */
0x1a8, /* MPHY_RX_APB_VENDOR11_0 */
0x1ac, /* MPHY_RX_APB_VENDOR12_0 */
0x1b0, /* MPHY_RX_APB_VENDOR13_0 */
0x1b4, /* MPHY_RX_APB_VENDOR14_0 */
0x1b8, /* MPHY_RX_APB_VENDOR15_0 */
0x1bc, /* MPHY_RX_APB_VENDOR16_0 */
0x1c0, /* MPHY_RX_APB_VENDOR17_0 */
0x1c4, /* MPHY_RX_APB_VENDOR18_0 */
0x1c8, /* MPHY_RX_APB_VENDOR19_0 */
0x1cc, /* MPHY_RX_APB_VENDOR20_0 */
0x1d0, /* MPHY_RX_APB_VENDOR21_0 */
0x1d4, /* MPHY_RX_APB_VENDOR22_0 */
0x1d8, /* MPHY_RX_APB_VENDOR23_0 */
0x1dc, /* MPHY_RX_APB_VENDOR24_0 */
0x1e0, /* MPHY_RX_APB_VENDOR25_0 */
0x1e4, /* MPHY_RX_APB_VENDOR26_0 */
0x1e8, /* MPHY_RX_APB_VENDOR27_0 */
0x1ec, /* MPHY_RX_APB_VENDOR28_0 */
0x1f0, /* MPHY_RX_APB_VENDOR29_0 */
0x1f4, /* MPHY_RX_APB_VENDOR30_0 */
0x1f8, /* MPHY_RX_APB_VENDOR31_0 */
0x1fc /* MPHY_RX_APB_VENDOR32_0 */
};
/*
* MPHY Context save armphy_tx_apb registers
*/
static u16 __attribute__ ((unused)) mphy_tx_apb[] = {
0x000, /* MPHY_TX_APB_TX_CAPABILITY_00_03_0 */
0x004, /* MPHY_TX_APB_TX_CAPABILITY_04_07_0 */
0x008, /* MPHY_TX_APB_TX_CAPABILITY_08_0B_0 */
0x00c, /* MPHY_TX_APB_TX_CAPABILITY_0C_0F_0 */
0x010, /* MPHY_TX_APB_TX_CAPABILITY_10_13_0 */
0x020, /* MPHY_TX_APB_TX_ATTRIBUTE_20_23_0 */
0x024, /* MPHY_TX_APB_TX_ATTRIBUTE_24_27_0 */
0x028, /* MPHY_TX_APB_TX_ATTRIBUTE_28_2B_0 */
0x02c, /* MPHY_TX_APB_TX_ATTRIBUTE_2C_2F_0 */
0x030, /* MPHY_TX_APB_TX_ATTRIBUTE_30_33_0 */
0x034, /* MPHY_TX_APB_TX_ATTRIBUTE_34_37_0 */
0x038, /* MPHY_TX_APB_TX_ATTRIBUTE_38_3B_0 */
0x060, /* MPHY_TX_APB_MC_ATTRIBUTE_60_63_0 */
0x064, /* MPHY_TX_APB_MC_ATTRIBUTE_64_67_0 */
0x100, /* MPHY_TX_APB_TX_VENDOR0_0 */
0x104, /* MPHY_TX_APB_TX_VENDOR1_0 */
0x108, /* MPHY_TX_APB_TX_VENDOR2_0 */
0x10c, /* MPHY_TX_APB_TX_VENDOR3_0 */
0x110, /* MPHY_TX_APB_TX_VENDOR4_0 */
0x114, /* MPHY_TX_APB_TX_VENDOR5_0 */
0x118, /* MPHY_TX_APB_TX_VENDOR6_0 */
0x11c, /* MPHY_TX_APB_TX_VENDOR7_0 */
0x120, /* MPHY_TX_APB_PAD_TIMING0_0 */
0x124, /* MPHY_TX_APB_PAD_TIMING1_0 */
0x128, /* MPHY_TX_APB_PAD_TIMING2_0 */
0x12c, /* MPHY_TX_APB_PAD_TIMING3_0 */
0x130, /* MPHY_TX_APB_PAD_TIMING4_0 */
0x134, /* MPHY_TX_APB_PAD_TIMING5_0 */
0x138, /* MPHY_TX_APB_PAD_TIMING6_0 */
0x13c, /* MPHY_TX_APB_PAD_TIMING7_0 */
0x140, /* MPHY_TX_APB_PAD_TIMING8_0 */
0x144, /* MPHY_TX_APB_PAD_TIMING9_0 */
0x148, /* MPHY_TX_APB_PAD_TIMING10_0 */
0x14c, /* MPHY_TX_APB_TX_PAD_OVR_VAL0_0 */
0x150, /* MPHY_TX_APB_TX_PAD_OVR_CTRL0_0 */
0x154, /* MPHY_TX_APB_TX_OVR_CTRL0_0 */
0x158, /* MPHY_TX_APB_TX_OVR_VAL0_0 */
0x15c, /* MPHY_TX_APB_PAD_TIMER0_0 */
0x160, /* MPHY_TX_APB_TX_CLK_CTRL0_0 */
0x164, /* MPHY_TX_APB_TX_CLK_CTRL1_0 */
0x168, /* MPHY_TX_APB_TX_CLK_CTRL2_0 */
0x16c, /* MPHY_TX_APB_TX_CLK_CTRL3_0 */
0x170, /* MPHY_TX_APB_TX_CG_OVR0_0 */
0x174, /* MPHY_TX_APB_TX_CG_COUNTER0_0 */
0x178, /* MPHY_TX_APB_TX_PAD_OVR_VAL1_0 */
0x17c /* MPHY_TX_APB_TX_PAD_OVR_CTRL1_0 */
};
struct ufs_tegra_soc_data {
u8 chip_id;
};
@@ -345,7 +225,6 @@ struct ufs_tegra_host {
struct ufs_hba *hba;
bool is_lane_clks_enabled;
bool x2config;
bool enable_mphy_rx_calib;
bool enable_hs_mode;
bool enable_38mhz_clk;
bool enable_ufs_provisioning;
@@ -400,11 +279,6 @@ struct ufs_tegra_host {
struct pinctrl_state *dpd_enable;
struct pinctrl_state *dpd_disable;
u32 vs_burst;
/* Hibernate entry support is broken
WAR is suggested to fix hibernate entry functionality
*/
#define NVQUIRK_BROKEN_HIBERN8_ENTRY UTP_TRANSFER_REQ_COMPL
/* UFS tegra deviations from standard UFSHCI spec. */
unsigned int nvquirks;
bool wake_enable_failed;
@@ -430,8 +304,6 @@ struct ufs_tegra_host {
};
extern struct ufs_hba_variant_ops ufs_hba_tegra_vops;
extern int ufshcd_rescan(struct ufs_hba *hb);
void ufs_rescan(struct work_struct *work);
static inline u32 mphy_readl(void __iomem *mphy_base, u32 offset)
{
@@ -451,8 +323,7 @@ static inline void mphy_writel(void __iomem *mphy_base, u32 val, u32 offset)
writel(val, mphy_base + offset);
}
static inline void mphy_update(void __iomem *mphy_base, u32 val,
u32 offset)
static inline void mphy_update(void __iomem *mphy_base, u32 val, u32 offset)
{
u32 update_val;
@@ -461,8 +332,7 @@ static inline void mphy_update(void __iomem *mphy_base, u32 val,
mphy_writel(mphy_base, update_val, offset);
}
static inline void mphy_clear_bits(void __iomem *mphy_base, u32 val,
u32 offset)
static inline void mphy_clear_bits(void __iomem *mphy_base, u32 val, u32 offset)
{
u32 update_val;