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gpu: host1x: Add SE SID entries for Tegra234.

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Add Security Engine Stream ID  entries in host1x SID table for
Tegra234.

Bug 3583641

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Change-Id: I5d96478aad8d24208bad92e61942a57c0fd5df1a
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2782822
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Akhil R
2022-09-27 15:54:13 +05:30
committed by Laxman Dewangan
parent f374e1804e
commit 128385051a
1 changed files with 37 additions and 1 deletions
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38
drivers/gpu/host1x/dev.c
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@@ -2,7 +2,7 @@
/*
* Tegra host1x driver
*
* Copyright (c) 2010-2022, NVIDIA Corporation.
* Copyright (c) 2010-2022, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
*/
#include <linux/clk.h>
@@ -256,6 +256,42 @@ static const struct host1x_info host1x07_info = {
* and firmware stream ID in the MMIO path table.
*/
static const struct host1x_sid_entry tegra234_sid_table[] = {
{
/* SE1 MMIO */
.base = 0x1650,
.offset = 0x90,
.limit = 0x90
},
{
/* SE2 MMIO */
.base = 0x1658,
.offset = 0x90,
.limit = 0x90
},
{
/* SE4 MMIO */
.base = 0x1660,
.offset = 0x90,
.limit = 0x90
},
{
/* SE1 channel */
.base = 0x1730,
.offset = 0x90,
.limit = 0x90
},
{
/* SE2 channel */
.base = 0x1738,
.offset = 0x90,
.limit = 0x90
},
{
/* SE4 channel */
.base = 0x1740,
.offset = 0x90,
.limit = 0x90
},
{
/* VIC channel */
.base = 0x17b8,