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drivers:nvpps: Add nvpps k5.10 updates to k5.15

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Add nvpps k5.10 updates to k5.15

Bug 3896607

Change-Id: Id9614ca9329804ae81d3d60e2f8647191208d2b6
Signed-off-by: Sheetal Tigadoli <stigadoli@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2877070
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sheetal Tigadoli
2023-03-26 14:09:46 +00:00
committed by mobile promotions
parent 61586ca1df
commit 182768fd7b
1 changed files with 41 additions and 4 deletions
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45
drivers/nvpps/nvpps_main.c
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@@ -1,8 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
@@ -92,6 +102,8 @@ struct nvpps_device_data {
bool only_timer_mode;
bool pri_ptp_failed;
bool sec_ptp_failed;
uint8_t k_int_val;
uint16_t lock_threshold_val;
};
@@ -129,6 +141,7 @@ struct nvpps_file_data {
#define TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET 0x10c
#define TSC_LOCKING_ADJUST_NUM_CONTROL_OFFSET 0x110
#define TSC_LOCKING_ADJUST_DELTA_CONTROL_OFFSET 0x114
#define TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET_K_INT_SHIFT 8
#define SRC_SELECT_BIT_OFFSET 8
#define SRC_SELECT_BITS 0xff
@@ -877,14 +890,38 @@ static void nvpps_fill_default_mac_phc_info(struct platform_device *pdev,
static void nvpps_ptp_tsc_sync_config(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
uint32_t tsc_config_ptx_0;
struct nvpps_device_data *pdev_data = platform_get_drvdata(pdev);
#define DEFAULT_K_INT_VAL 0x70
#define DEFAULT_LOCK_THRESHOLD_20US 0x26c
//Set default K_INT & LOCK Threshold value
pdev_data->k_int_val = DEFAULT_K_INT_VAL;
pdev_data->lock_threshold_val = DEFAULT_LOCK_THRESHOLD_20US;
//Override default K_INT value
if (of_property_read_u8(np, "ptp_tsc_k_int", &pdev_data->k_int_val) == 0) {
dev_info(&pdev->dev, "Using K_INT value : 0x%x\n", pdev_data->k_int_val);
}
//Override default Lock Threshold value
if (of_property_read_u16(np, "ptp_tsc_lock_threshold", &pdev_data->lock_threshold_val) == 0) {
if (pdev_data->lock_threshold_val < 0x1F) {
//Use default value
dev_warn(&pdev->dev, "ptp_tsc_lock_threshold value should be minimum 1us(i.e 0x1F). Using default value 20us(i.e 0x26c)\n");
pdev_data->lock_threshold_val = DEFAULT_LOCK_THRESHOLD_20US;
}
dev_info(&pdev->dev, "Using Lock threshold value : 0x%x\n", pdev_data->lock_threshold_val);
}
//onetime config to init PTP TSC Sync logic
writel(0x119, pdev_data->tsc_reg_map_base + TSC_LOCKING_CONFIGURATION_OFFSET);
writel(0x26c, pdev_data->tsc_reg_map_base + TSC_LOCKING_DIFF_CONFIGURATION_OFFSET);
writel(pdev_data->lock_threshold_val, pdev_data->tsc_reg_map_base + TSC_LOCKING_DIFF_CONFIGURATION_OFFSET);
writel(0x1, pdev_data->tsc_reg_map_base + TSC_LOCKING_CONTROL_OFFSET);
writel(0x57011, pdev_data->tsc_reg_map_base + TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET);
writel((0x50011 | (pdev_data->k_int_val << TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET_K_INT_SHIFT)),
pdev_data->tsc_reg_map_base + TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET);
writel(0x67, pdev_data->tsc_reg_map_base + TSC_LOCKING_ADJUST_DELTA_CONTROL_OFFSET);
writel(0x313, pdev_data->tsc_reg_map_base + TSC_CAPTURE_CONFIGURATION_PTX_OFFSET);
writel(0x1, pdev_data->tsc_reg_map_base + TSC_STSCRSR_OFFSET);