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r8168: Fix -20C 10mbps failure in Mods test

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Issue:
Ethernet mplan stability tests at -20C for 10Mbps fails with rate 15%
Basically the GPHY 10M power saving includes the below parameters,
clock speed down, pll off and reference voltage off.
During debugging it was found that enable/disable pll circuit
frequently when in 10M low data traffic (such as idle mode) may have
a corner case and plays a part in this issue repro.

Fix:
So plloff saving function should be disable (do not have to open it) for nvidia -20C mplan test case.

Bug 3946623

Change-Id: Ifabe9e26e840537520d66acca106b37d3c285722
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3123359
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Revanth Kumar Uppala
2024-04-24 16:48:23 +05:30
committed by mobile promotions
parent ae13276f5d
commit 20dbe0996b
1 changed files with 12 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/net/ethernet/realtek/r8168/r8168_n.c
View File

@@ -25331,7 +25331,10 @@ rtl8168_hw_phy_config(struct net_device *dev)
}
rtl8168_mdio_write(tp, 0x1F, 0x0A44);
rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11);
rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7));
rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11));
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0));
rtl8168_mdio_write(tp, 0x1F, 0x0000);
@@ -25383,7 +25386,10 @@ rtl8168_hw_phy_config(struct net_device *dev)
}
rtl8168_mdio_write(tp, 0x1F, 0x0A44);
rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11);
rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7));
rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11));
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0));
rtl8168_mdio_write(tp, 0x1F, 0x0000);
if (tp->RequireAdcBiasPatch) {
@@ -25588,7 +25594,10 @@ rtl8168_hw_phy_config(struct net_device *dev)
}
} else if (tp->mcfg == CFG_METHOD_35) {
rtl8168_mdio_write(tp, 0x1F, 0x0A44);
rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11);
rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7));
rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11));
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0));
rtl8168_mdio_write(tp, 0x1F, 0x0000);