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drm/tegra: nvdec: Fix TRANSCFG register offset

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NVDEC's TRANSCFG register is at a different offset than VIC.
This becomes a problem now when context isolation is enabled and
the reset value of the register is no longer sufficient.

Bug 3724727

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: Ic83043dcc49a3739fe310cfb5b143b42d9aa259b
This commit is contained in:
Mikko Perttunen
2022-05-20 08:35:06 +03:00
committed by Laxman Dewangan
parent abbdd9c844
commit 250d164381
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/tegra/nvdec.c
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@@ -21,6 +21,8 @@
#include "falcon.h"
#include "vic.h"
#define NVDEC_TFBIF_TRANSCFG 0x2c44
struct nvdec_config {
const char *firmware;
unsigned int version;
@@ -63,7 +65,7 @@ static int nvdec_boot(struct nvdec *nvdec)
u32 value;
value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW);
nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG);
nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);
if (spec->num_ids > 0) {
value = spec->ids[0] & 0xffff;