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crypto: increase buffer support for SHA operation
Using this patches we are making below changes:- 1. increase buffer support for SHA operation from 1MB to 2MB 2. get the IVC DB during init call. Bug 4141706 Change-Id: I8101430117569049f3420db58ed06e0158cc2dcc Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2984637 Reviewed-by: Advaya Andhare <aandhare@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -43,7 +43,7 @@
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#define SE_MAX_SCHEDULE_TIMEOUT LONG_MAX
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#define SE_MAX_SCHEDULE_TIMEOUT LONG_MAX
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#define TEGRA_HV_VSE_SHA_MAX_LL_NUM_1 1
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#define TEGRA_HV_VSE_SHA_MAX_LL_NUM_1 1
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#define TEGRA_HV_VSE_AES_CMAC_MAX_LL_NUM 1
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#define TEGRA_HV_VSE_AES_CMAC_MAX_LL_NUM 2
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#define TEGRA_HV_VSE_MAX_TASKS_PER_SUBMIT 1
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#define TEGRA_HV_VSE_MAX_TASKS_PER_SUBMIT 1
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#define TEGRA_HV_VSE_TIMEOUT (msecs_to_jiffies(10000))
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#define TEGRA_HV_VSE_TIMEOUT (msecs_to_jiffies(10000))
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#define TEGRA_HV_VSE_SHA_MAX_BLOCK_SIZE 128
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#define TEGRA_HV_VSE_SHA_MAX_BLOCK_SIZE 128
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@@ -74,6 +74,8 @@ struct nvvse_devnode {
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bool sha_init_done;
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bool sha_init_done;
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} nvvse_devnode[MAX_NUMBER_MISC_DEVICES];
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} nvvse_devnode[MAX_NUMBER_MISC_DEVICES];
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static struct tegra_nvvse_get_ivc_db ivc_database;
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/* SHA Algorithm Names */
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/* SHA Algorithm Names */
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static const char *sha_alg_names[] = {
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static const char *sha_alg_names[] = {
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"sha256-vse",
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"sha256-vse",
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@@ -462,6 +464,12 @@ static int tnvvse_crypto_sha_update(struct tnvvse_crypto_ctx *ctx,
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char *input_buffer = update_ctl->in_buff;
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char *input_buffer = update_ctl->in_buff;
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int ret;
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int ret;
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if (update_ctl->input_buffer_size > ivc_database.max_buffer_size[ctx->node_id]) {
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pr_err("%s: Msg size is greater than supported size of %d Bytes\n", __func__,
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ivc_database.max_buffer_size[ctx->node_id]);
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return -EINVAL;
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}
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result_buff = sha_state->result_buff;
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result_buff = sha_state->result_buff;
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req = sha_state->req;
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req = sha_state->req;
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@@ -1879,7 +1887,6 @@ static long tnvvse_crypto_dev_ioctl(struct file *filp,
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struct tegra_nvvse_aes_drng_ctl *aes_drng_ctl;
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struct tegra_nvvse_aes_drng_ctl *aes_drng_ctl;
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struct tegra_nvvse_aes_gmac_init_ctl *aes_gmac_init_ctl;
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struct tegra_nvvse_aes_gmac_init_ctl *aes_gmac_init_ctl;
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struct tegra_nvvse_aes_gmac_sign_verify_ctl *aes_gmac_sign_verify_ctl;
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struct tegra_nvvse_aes_gmac_sign_verify_ctl *aes_gmac_sign_verify_ctl;
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struct tegra_nvvse_get_ivc_db *get_ivc_db;
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struct tegra_nvvse_tsec_get_keyload_status *tsec_keyload_status;
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struct tegra_nvvse_tsec_get_keyload_status *tsec_keyload_status;
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int ret = 0;
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int ret = 0;
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@@ -2119,27 +2126,12 @@ static long tnvvse_crypto_dev_ioctl(struct file *filp,
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break;
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break;
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case NVVSE_IOCTL_CMDID_GET_IVC_DB:
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case NVVSE_IOCTL_CMDID_GET_IVC_DB:
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get_ivc_db = kzalloc(sizeof(*get_ivc_db), GFP_KERNEL);
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ret = copy_to_user((void __user *)arg, &ivc_database, sizeof(ivc_database));
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if (!get_ivc_db) {
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pr_err("%s(): failed to allocate memory\n", __func__);
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return -ENOMEM;
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}
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ret = tnvvse_crypto_get_ivc_db(get_ivc_db);
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if (ret) {
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if (ret) {
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pr_err("%s(): Failed to get ivc database get_ivc_db:%d\n", __func__, ret);
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pr_err("%s(): Failed to copy_to_user ivc_database:%d\n", __func__, ret);
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kfree(get_ivc_db);
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goto out;
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goto out;
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}
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}
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ret = copy_to_user((void __user *)arg, get_ivc_db, sizeof(*get_ivc_db));
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if (ret) {
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pr_err("%s(): Failed to copy_to_user get_ivc_db:%d\n", __func__, ret);
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kfree(get_ivc_db);
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goto out;
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}
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kfree(get_ivc_db);
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break;
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break;
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case NVVSE_IOCTL_CMDID_TSEC_SIGN_VERIFY:
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case NVVSE_IOCTL_CMDID_TSEC_SIGN_VERIFY:
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@@ -2226,6 +2218,9 @@ static int __init tnvvse_crypto_device_init(void)
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int ret = 0;
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int ret = 0;
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struct miscdevice *misc;
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struct miscdevice *misc;
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/* get ivc databse */
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tnvvse_crypto_get_ivc_db(&ivc_database);
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for (cnt = 0; cnt < MAX_NUMBER_MISC_DEVICES; cnt++) {
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for (cnt = 0; cnt < MAX_NUMBER_MISC_DEVICES; cnt++) {
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/* Dynamic initialisation of misc device */
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/* Dynamic initialisation of misc device */
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