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crypto: tegra: Deprecate Tegra Nvhost driver for k5.15
Remove Tegra SE Nvhost driver to deprecate the support for T186 and T194 Security Engines in kernel-5.15. Bug 4221414 Bug 3579794 Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Change-Id: I425bc7068f2139e73dd14f0187d10ea856260cac Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2984417 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Akhil R
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@@ -83,8 +83,8 @@ BUILT_MODULE_NAME[19]="tegra-pcie-dma-test"
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BUILT_MODULE_LOCATION[19]="drivers/misc"
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DEST_MODULE_LOCATION[19]="/extra"
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BUILT_MODULE_NAME[20]="tegra-se-nvhost"
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BUILT_MODULE_LOCATION[20]="drivers/crypto"
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BUILT_MODULE_NAME[20]="tegra-se"
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BUILT_MODULE_LOCATION[20]="drivers/crypto/tegra"
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DEST_MODULE_LOCATION[20]="/extra"
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BUILT_MODULE_NAME[21]="tegra-se-nvrng"
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@@ -2,7 +2,6 @@
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# Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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ifdef CONFIG_TEGRA_HOST1X
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obj-m += tegra-se-nvhost.o
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obj-m += tegra-hv-vse-safety.o
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obj-m += tegra-nvvse-cryptodev.o
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ifdef CONFIG_CRYPTO_ENGINE
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@@ -1,163 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Tegra T194 HOST1X Register Definitions
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*/
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#ifndef __NVHOST_HARDWARE_T194_H
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#define __NVHOST_HARDWARE_T194_H
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#include <hw_host1x05_sync.h>
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#include <hw_host1x06_uclass.h>
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#include <hw_host1x06_channel.h>
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/* sync registers */
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#define NV_HOST1X_SYNCPT_NB_PTS 704
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#define NV_HOST1X_NB_MLOCKS 32
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#define NV_HOST1X_MLOCK_ID_NVCSI 7
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#define NV_HOST1X_MLOCK_ID_ISP 8
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#define NV_HOST1X_MLOCK_ID_VI 16
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#define NV_HOST1X_MLOCK_ID_VIC 17
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#define NV_HOST1X_MLOCK_ID_NVENC 18
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#define NV_HOST1X_MLOCK_ID_NVDEC 19
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#define NV_HOST1X_MLOCK_ID_NVJPG 20
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#define NV_HOST1X_MLOCK_ID_TSEC 21
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#define NV_HOST1X_MLOCK_ID_TSECB 22
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#define NV_HOST1X_MLOCK_ID_NVENC1 29
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#define NV_HOST1X_MLOCK_ID_NVDEC1 31
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#define HOST1X_THOST_ACTMON_NVENC 0x00000
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#define HOST1X_THOST_ACTMON_VIC 0x10000
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#define HOST1X_THOST_ACTMON_NVDEC 0x20000
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#define HOST1X_THOST_ACTMON_NVJPG 0x30000
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#define HOST1X_THOST_ACTMON_NVENC1 0x40000
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#define HOST1X_THOST_ACTMON_NVDEC1 0x50000
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/* Generic support */
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static inline u32 nvhost_class_host_wait_syncpt(
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unsigned indx, unsigned threshold)
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{
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return (indx << 24) | (threshold & 0xffffff);
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}
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static inline u32 nvhost_class_host_load_syncpt_base(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_wait_syncpt_indx_f(indx)
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| host1x_uclass_wait_syncpt_thresh_f(threshold);
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}
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static inline u32 nvhost_class_host_incr_syncpt(
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unsigned cond, unsigned indx)
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{
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return host1x_uclass_incr_syncpt_cond_f(cond)
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| host1x_uclass_incr_syncpt_indx_f(indx);
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}
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enum {
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NV_HOST_MODULE_HOST1X = 0,
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NV_HOST_MODULE_MPE = 1,
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NV_HOST_MODULE_GR3D = 6
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};
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/* cdma opcodes */
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static inline u32 nvhost_opcode_setclass(
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unsigned class_id, unsigned offset, unsigned mask)
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{
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return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
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}
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static inline u32 nvhost_opcode_incr(unsigned offset, unsigned count)
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{
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return (1 << 28) | (offset << 16) | count;
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}
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static inline u32 nvhost_opcode_nonincr(unsigned offset, unsigned count)
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{
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return (2 << 28) | (offset << 16) | count;
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}
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static inline u32 nvhost_opcode_mask(unsigned offset, unsigned mask)
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{
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return (3 << 28) | (offset << 16) | mask;
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}
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static inline u32 nvhost_opcode_imm(unsigned offset, unsigned value)
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{
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return (4 << 28) | (offset << 16) | value;
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}
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static inline u32 nvhost_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
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{
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return nvhost_opcode_imm(host1x_uclass_incr_syncpt_r(),
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nvhost_class_host_incr_syncpt(cond, indx));
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}
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static inline u32 nvhost_opcode_restart(unsigned address)
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{
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return (5 << 28) | (address >> 4);
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}
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static inline u32 nvhost_opcode_gather(unsigned count)
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{
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return (6 << 28) | count;
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}
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static inline u32 nvhost_opcode_gather_nonincr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | count;
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}
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static inline u32 nvhost_opcode_gather_incr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
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}
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static inline u32 nvhost_opcode_gather_insert(unsigned offset, unsigned incr,
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unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | (incr << 14) | count;
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}
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static inline u32 nvhost_opcode_setstreamid(unsigned streamid)
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{
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return (7 << 28) | streamid;
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}
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static inline u32 nvhost_opcode_setpayload(unsigned payload)
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{
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return (9 << 28) | payload;
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}
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static inline u32 nvhost_opcode_acquire_mlock(unsigned id)
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{
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return (14 << 28) | id;
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}
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static inline u32 nvhost_opcode_release_mlock(unsigned id)
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{
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return (14 << 28) | (1 << 24) | id;
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}
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static inline u32 nvhost_opcode_incr_w(unsigned int offset)
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{
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/* 22-bit offset supported */
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return (10 << 28) | offset;
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}
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static inline u32 nvhost_opcode_nonincr_w(unsigned offset)
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{
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/* 22-bit offset supported */
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return (11 << 28) | offset;
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}
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#define NVHOST_OPCODE_NOOP nvhost_opcode_nonincr(0, 0)
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static inline u32 nvhost_mask2(unsigned x, unsigned y)
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{
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return 1 | (1 << (y - x));
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}
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#endif /* __NVHOST_HARDWARE_T194_H */
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@@ -1,937 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2009-2023, NVIDIA Corporation. All rights reserved.
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*
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* Tegra graphics host driver
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*/
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#ifndef __LINUX_NVHOST_H
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#define __LINUX_NVHOST_H
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#include <linux/cdev.h>
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#include <linux/device.h>
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#include <linux/types.h>
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#include <linux/devfreq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_qos.h>
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#include <linux/time.h>
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#include <linux/version.h>
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//#include <uapi/linux/nvdev_fence.h>
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#ifdef CONFIG_TEGRA_HOST1X
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#include <linux/host1x.h>
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#endif
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#if IS_ENABLED(CONFIG_TEGRA_GRHOST) && IS_ENABLED(CONFIG_TEGRA_HOST1X)
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#error "Unable to enable TEGRA_GRHOST or TEGRA_HOST1X at the same time!"
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#endif
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struct tegra_bwmgr_client;
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struct nvhost_channel;
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struct nvhost_master;
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struct nvhost_cdma;
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struct nvhost_hwctx;
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struct nvhost_device_power_attr;
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struct nvhost_device_profile;
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struct mem_mgr;
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struct nvhost_as_moduleops;
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struct nvhost_ctrl_sync_fence_info;
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struct nvhost_sync_timeline;
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struct nvhost_sync_pt;
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enum nvdev_fence_kind;
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struct nvdev_fence;
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struct sync_pt;
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struct dma_fence;
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struct nvhost_fence;
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#define NVHOST_MODULE_MAX_CLOCKS 8
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#define NVHOST_MODULE_MAX_SYNCPTS 16
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#define NVHOST_MODULE_MAX_WAITBASES 3
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#define NVHOST_MODULE_MAX_MODMUTEXES 5
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#define NVHOST_MODULE_MAX_IORESOURCE_MEM 5
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#define NVHOST_NAME_SIZE 24
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#define NVSYNCPT_INVALID (-1)
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#define NVSYNCPT_AVP_0 (10) /* t20, t30, t114, t148 */
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#define NVSYNCPT_3D (22) /* t20, t30, t114, t148 */
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#define NVSYNCPT_VBLANK0 (26) /* t20, t30, t114, t148 */
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#define NVSYNCPT_VBLANK1 (27) /* t20, t30, t114, t148 */
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#define NVMODMUTEX_ISP_0 (1) /* t124, t132, t210 */
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#define NVMODMUTEX_ISP_1 (2) /* t124, t132, t210 */
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#define NVMODMUTEX_NVJPG (3) /* t210 */
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#define NVMODMUTEX_NVDEC (4) /* t210 */
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#define NVMODMUTEX_MSENC (5) /* t124, t132, t210 */
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#define NVMODMUTEX_TSECA (6) /* t124, t132, t210 */
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#define NVMODMUTEX_TSECB (7) /* t124, t132, t210 */
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#define NVMODMUTEX_VI (8) /* t124, t132, t210 */
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#define NVMODMUTEX_VI_0 (8) /* t148 */
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#define NVMODMUTEX_VIC (10) /* t124, t132, t210 */
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#define NVMODMUTEX_VI_1 (11) /* t124, t132, t210 */
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enum nvhost_power_sysfs_attributes {
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NVHOST_POWER_SYSFS_ATTRIB_AUTOSUSPEND_DELAY,
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NVHOST_POWER_SYSFS_ATTRIB_FORCE_ON,
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NVHOST_POWER_SYSFS_ATTRIB_MAX
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};
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struct nvhost_notification {
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struct { /* 0000- */
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__u32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 */
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} time_stamp; /* -0007 */
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__u32 info32; /* info returned depends on method 0008-000b */
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#define NVHOST_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8
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#define NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY 13
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#define NVHOST_CHANNEL_GR_SEMAPHORE_TIMEOUT 24
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#define NVHOST_CHANNEL_GR_ILLEGAL_NOTIFY 25
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#define NVHOST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31
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#define NVHOST_CHANNEL_PBDMA_ERROR 32
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#define NVHOST_CHANNEL_RESETCHANNEL_VERIF_ERROR 43
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__u16 info16; /* info returned depends on method 000c-000d */
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__u16 status; /* user sets bit 15, NV sets status 000e-000f */
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#define NVHOST_CHANNEL_SUBMIT_TIMEOUT 1
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};
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struct nvhost_gating_register {
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u64 addr;
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u32 prod;
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u32 disable;
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};
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struct nvhost_actmon_register {
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u32 addr;
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u32 val;
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};
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enum tegra_emc_request_type {
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TEGRA_SET_EMC_FLOOR, /* lower bound */
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TEGRA_SET_EMC_CAP, /* upper bound */
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TEGRA_SET_EMC_ISO_CAP, /* upper bound that affects ISO Bw */
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TEGRA_SET_EMC_SHARED_BW, /* shared bw request */
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TEGRA_SET_EMC_SHARED_BW_ISO, /* for use by ISO Mgr only */
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TEGRA_SET_EMC_REQ_COUNT /* Should always be last */
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};
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struct nvhost_clock {
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char *name;
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unsigned long default_rate;
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u32 moduleid;
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enum tegra_emc_request_type request_type;
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bool disable_scaling;
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unsigned long devfreq_rate;
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};
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struct nvhost_vm_hwid {
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u64 addr;
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bool dynamic;
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u32 shift;
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};
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/*
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* Defines HW and SW class identifiers.
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*
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* This is module ID mapping between userspace and kernelspace.
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* The values of enum entries' are referred from NvRmModuleID enum defined
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* in below userspace file:
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* $TOP/vendor/nvidia/tegra/core/include/nvrm_module.h
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* Please make sure each entry below has same value as set in above file.
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*/
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enum nvhost_module_identifier {
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/* Specifies external memory (DDR RAM, etc) */
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER = 75,
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/* Specifies CBUS floor client module */
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NVHOST_MODULE_ID_CBUS_FLOOR = 119,
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/* Specifies shared EMC client module */
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NVHOST_MODULE_ID_EMC_SHARED,
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NVHOST_MODULE_ID_MAX
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};
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enum nvhost_resource_policy {
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RESOURCE_PER_DEVICE = 0,
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RESOURCE_PER_CHANNEL_INSTANCE,
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};
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struct nvhost_device_data {
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int version; /* ip version number of device */
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int id; /* Separates clients of same hw */
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void __iomem *aperture[NVHOST_MODULE_MAX_IORESOURCE_MEM];
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struct device_dma_parameters dma_parms;
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u32 modulemutexes[NVHOST_MODULE_MAX_MODMUTEXES];
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u32 moduleid; /* Module id for user space API */
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/* interrupt ISR routine for falcon based engines */
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int (*flcn_isr)(struct platform_device *dev);
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int irq;
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int module_irq; /* IRQ bit from general intr reg for module intr */
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spinlock_t mirq_lock; /* spin lock for module irq */
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bool self_config_flcn_isr; /* skip setting up falcon interrupts */
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/* Should we toggle the engine SLCG when we turn on the domain? */
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bool poweron_toggle_slcg;
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/* Flag to set SLCG notifier (for the modules other than VIC) */
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bool slcg_notifier_enable;
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/* Used to serialize channel when map-at-submit is used w/o mlocks */
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u32 last_submit_syncpt_id;
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u32 last_submit_syncpt_value;
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bool power_on; /* If module is powered on */
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u32 class; /* Device class */
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bool exclusive; /* True if only one user at a time */
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bool keepalive; /* Do not power gate when opened */
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bool serialize; /* Serialize submits in the channel */
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bool push_work_done; /* Push_op done into push buffer */
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bool poweron_reset; /* Reset the engine before powerup */
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bool virtual_dev; /* True if virtualized device */
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char *devfs_name; /* Name in devfs */
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char *devfs_name_family; /* Core of devfs name */
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/* Support aborting the channel with close(channel_fd) */
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bool support_abort_on_close;
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char *firmware_name; /* Name of firmware */
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bool firmware_not_in_subdir; /* Firmware is not located in
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chip subdirectory */
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bool engine_can_cg; /* True if CG is enabled */
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bool can_powergate; /* True if module can be power gated */
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int autosuspend_delay;/* Delay before power gated */
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struct nvhost_clock clocks[NVHOST_MODULE_MAX_CLOCKS];/* Clock names */
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/* Clock gating registers */
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struct nvhost_gating_register *engine_cg_regs;
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int num_clks; /* Number of clocks opened for dev */
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#if IS_ENABLED(CONFIG_TEGRA_GRHOST)
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struct clk *clk[NVHOST_MODULE_MAX_CLOCKS];
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#else
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struct clk_bulk_data *clks;
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#endif
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struct mutex lock; /* Power management lock */
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struct list_head client_list; /* List of clients and rate requests */
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int num_channels; /* Max num of channel supported */
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int num_mapped_chs; /* Num of channel mapped to device */
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int num_ppc; /* Number of pixels per clock cycle */
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/* device node for channel operations */
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dev_t cdev_region;
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struct device *node;
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struct cdev cdev;
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/* Address space device node */
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struct device *as_node;
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struct cdev as_cdev;
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/* device node for ctrl block */
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struct class *nvhost_class;
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struct device *ctrl_node;
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struct cdev ctrl_cdev;
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const struct file_operations *ctrl_ops; /* ctrl ops for the module */
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/* address space operations */
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const struct nvhost_as_moduleops *as_ops;
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struct kobject *power_kobj; /* kobject to hold power sysfs entries */
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struct nvhost_device_power_attr *power_attrib; /* sysfs attributes */
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/* kobject to hold clk_cap sysfs entries */
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struct kobject clk_cap_kobj;
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struct kobj_attribute *clk_cap_attrs;
|
||||
struct dentry *debugfs; /* debugfs directory */
|
||||
|
||||
u32 nvhost_timeout_default;
|
||||
|
||||
/* Data for devfreq usage */
|
||||
struct devfreq *power_manager;
|
||||
/* Private device profile data */
|
||||
struct nvhost_device_profile *power_profile;
|
||||
/* Should we read load estimate from hardware? */
|
||||
bool actmon_enabled;
|
||||
/* Should we do linear emc scaling? */
|
||||
bool linear_emc;
|
||||
/* Offset to actmon registers */
|
||||
u32 actmon_regs;
|
||||
/* WEIGHT_COUNT of actmon */
|
||||
u32 actmon_weight_count;
|
||||
struct nvhost_actmon_register *actmon_setting_regs;
|
||||
/* Devfreq governor name */
|
||||
const char *devfreq_governor;
|
||||
unsigned long *freq_table;
|
||||
|
||||
/* Marks if the device is booted when pm runtime is disabled */
|
||||
bool booted;
|
||||
|
||||
/* Should be marked as true if nvhost shouldn't create device nodes */
|
||||
bool kernel_only;
|
||||
|
||||
void *private_data; /* private platform data */
|
||||
void *falcon_data; /* store the falcon info */
|
||||
struct platform_device *pdev; /* owner platform_device */
|
||||
void *virt_priv; /* private data for virtualized dev */
|
||||
#if IS_ENABLED(CONFIG_TEGRA_HOST1X)
|
||||
struct host1x *host1x; /* host1x device */
|
||||
#endif
|
||||
|
||||
struct mutex no_poweroff_req_mutex;
|
||||
struct dev_pm_qos_request no_poweroff_req;
|
||||
int no_poweroff_req_count;
|
||||
|
||||
struct notifier_block toggle_slcg_notifier;
|
||||
|
||||
struct rw_semaphore busy_lock;
|
||||
bool forced_idle;
|
||||
|
||||
/* Finalize power on. Can be used for context restore. */
|
||||
int (*finalize_poweron)(struct platform_device *dev);
|
||||
|
||||
/* Called each time we enter the class */
|
||||
int (*init_class_context)(struct platform_device *dev,
|
||||
struct nvhost_cdma *cdma);
|
||||
|
||||
/*
|
||||
* Reset the unit. Used for timeout recovery, resetting the unit on
|
||||
* probe and when un-powergating.
|
||||
*/
|
||||
void (*reset)(struct platform_device *dev);
|
||||
|
||||
/* Device is busy. */
|
||||
void (*busy)(struct platform_device *);
|
||||
|
||||
/* Device is idle. */
|
||||
void (*idle)(struct platform_device *);
|
||||
|
||||
/* Scaling init is run on device registration */
|
||||
void (*scaling_init)(struct platform_device *dev);
|
||||
|
||||
/* Scaling deinit is called on device unregistration */
|
||||
void (*scaling_deinit)(struct platform_device *dev);
|
||||
|
||||
/* Postscale callback is called after frequency change */
|
||||
void (*scaling_post_cb)(struct nvhost_device_profile *profile,
|
||||
unsigned long freq);
|
||||
|
||||
/* Preparing for power off. Used for context save. */
|
||||
int (*prepare_poweroff)(struct platform_device *dev);
|
||||
|
||||
/* paring for power off. Used for context save. */
|
||||
int (*aggregate_constraints)(struct platform_device *dev,
|
||||
int clk_index,
|
||||
unsigned long floor_rate,
|
||||
unsigned long pixel_rate,
|
||||
unsigned long bw_rate);
|
||||
|
||||
/* Called after successful client device init. This can
|
||||
* be used in cases where the hardware specifics differ
|
||||
* between hardware revisions */
|
||||
int (*hw_init)(struct platform_device *dev);
|
||||
|
||||
/* Used to add platform specific masks on reloc address */
|
||||
dma_addr_t (*get_reloc_phys_addr)(dma_addr_t phys_addr, u32 reloc_type);
|
||||
|
||||
/* Allocates a context handler for the device */
|
||||
struct nvhost_hwctx_handler *(*alloc_hwctx_handler)(u32 syncpt,
|
||||
struct nvhost_channel *ch);
|
||||
|
||||
/* engine specific init functions */
|
||||
int (*pre_virt_init)(struct platform_device *pdev);
|
||||
int (*post_virt_init)(struct platform_device *pdev);
|
||||
|
||||
/* engine specific functions */
|
||||
int (*memory_init)(struct platform_device *pdev);
|
||||
|
||||
phys_addr_t carveout_addr;
|
||||
phys_addr_t carveout_size;
|
||||
|
||||
/* Information related to engine-side synchronization */
|
||||
void *syncpt_unit_interface;
|
||||
|
||||
u64 transcfg_addr;
|
||||
u32 transcfg_val;
|
||||
u64 mamask_addr;
|
||||
u32 mamask_val;
|
||||
u64 borps_addr;
|
||||
u32 borps_val;
|
||||
struct nvhost_vm_hwid vm_regs[13];
|
||||
|
||||
/* Actmon IRQ from hintstatus_r */
|
||||
unsigned int actmon_irq;
|
||||
|
||||
/* Is the device already forced on? */
|
||||
bool forced_on;
|
||||
|
||||
/* Should we map channel at submit time? */
|
||||
bool resource_policy;
|
||||
|
||||
/* Should we enable context isolation for this device? */
|
||||
bool isolate_contexts;
|
||||
|
||||
/* channel user context list */
|
||||
struct mutex userctx_list_lock;
|
||||
struct list_head userctx_list;
|
||||
|
||||
/* reset control for this device */
|
||||
struct reset_control *reset_control;
|
||||
|
||||
/* For loadable nvgpu module, we dynamically assign function
|
||||
* pointer of gk20a_debug_dump_device once the module loads */
|
||||
void *debug_dump_data;
|
||||
void (*debug_dump_device)(void *dev);
|
||||
|
||||
/* icc client id for emc requests */
|
||||
int icc_id;
|
||||
|
||||
/* icc_path handle handle */
|
||||
struct icc_path *icc_path_handle;
|
||||
|
||||
/* bandwidth manager client id for emc requests */
|
||||
int bwmgr_client_id;
|
||||
|
||||
/* bandwidth manager handle */
|
||||
struct tegra_bwmgr_client *bwmgr_handle;
|
||||
|
||||
/* number of frames mlock can be locked for */
|
||||
u32 mlock_timeout_factor;
|
||||
|
||||
/* eventlib id for the device */
|
||||
int eventlib_id;
|
||||
|
||||
/* deliver task timestamps for falcon */
|
||||
void (*enable_timestamps)(struct platform_device *pdev,
|
||||
struct nvhost_cdma *cdma, dma_addr_t timestamp_addr);
|
||||
|
||||
/* enable risc-v boot */
|
||||
bool enable_riscv_boot;
|
||||
|
||||
/* store the risc-v info */
|
||||
void *riscv_data;
|
||||
|
||||
/* name of riscv descriptor binary */
|
||||
char *riscv_desc_bin;
|
||||
|
||||
/* name of riscv image binary */
|
||||
char *riscv_image_bin;
|
||||
|
||||
};
|
||||
|
||||
|
||||
static inline
|
||||
struct nvhost_device_data *nvhost_get_devdata(struct platform_device *pdev)
|
||||
{
|
||||
return (struct nvhost_device_data *)platform_get_drvdata(pdev);
|
||||
}
|
||||
|
||||
static inline bool nvhost_dev_is_virtual(struct platform_device *pdev)
|
||||
{
|
||||
struct nvhost_device_data *pdata = platform_get_drvdata(pdev);
|
||||
|
||||
return pdata->virtual_dev;
|
||||
}
|
||||
|
||||
struct nvhost_device_power_attr {
|
||||
struct platform_device *ndev;
|
||||
struct kobj_attribute power_attr[NVHOST_POWER_SYSFS_ATTRIB_MAX];
|
||||
};
|
||||
|
||||
int flcn_intr_init(struct platform_device *pdev);
|
||||
int flcn_reload_fw(struct platform_device *pdev);
|
||||
int nvhost_flcn_prepare_poweroff(struct platform_device *pdev);
|
||||
int nvhost_flcn_finalize_poweron(struct platform_device *dev);
|
||||
|
||||
/* common runtime pm and power domain APIs */
|
||||
int nvhost_module_init(struct platform_device *ndev);
|
||||
void nvhost_module_deinit(struct platform_device *dev);
|
||||
void nvhost_module_reset(struct platform_device *dev, bool reboot);
|
||||
void nvhost_module_idle(struct platform_device *dev);
|
||||
void nvhost_module_idle_mult(struct platform_device *pdev, int refs);
|
||||
int nvhost_module_busy(struct platform_device *dev);
|
||||
extern const struct dev_pm_ops nvhost_module_pm_ops;
|
||||
|
||||
void host1x_writel(struct platform_device *dev, u32 r, u32 v);
|
||||
u32 host1x_readl(struct platform_device *dev, u32 r);
|
||||
|
||||
/* common device management APIs */
|
||||
int nvhost_client_device_get_resources(struct platform_device *dev);
|
||||
int nvhost_client_device_release(struct platform_device *dev);
|
||||
int nvhost_client_device_init(struct platform_device *dev);
|
||||
|
||||
/* public host1x sync-point management APIs */
|
||||
u32 nvhost_get_syncpt_host_managed(struct platform_device *pdev,
|
||||
u32 param, const char *syncpt_name);
|
||||
void nvhost_syncpt_put_ref_ext(struct platform_device *pdev, u32 id);
|
||||
bool nvhost_syncpt_is_valid_pt_ext(struct platform_device *dev, u32 id);
|
||||
void nvhost_syncpt_set_minval(struct platform_device *dev, u32 id, u32 val);
|
||||
void nvhost_syncpt_set_min_update(struct platform_device *pdev, u32 id, u32 val);
|
||||
u32 nvhost_syncpt_read_maxval(struct platform_device *dev, u32 id);
|
||||
u32 nvhost_syncpt_incr_max_ext(struct platform_device *dev, u32 id, u32 incrs);
|
||||
int nvhost_syncpt_is_expired_ext(struct platform_device *dev, u32 id,
|
||||
u32 thresh);
|
||||
dma_addr_t nvhost_syncpt_address(struct platform_device *engine_pdev, u32 id);
|
||||
int nvhost_syncpt_unit_interface_init(struct platform_device *pdev);
|
||||
|
||||
/* public host1x interrupt management APIs */
|
||||
int nvhost_intr_register_notifier(struct platform_device *pdev,
|
||||
u32 id, u32 thresh,
|
||||
void (*callback)(void *, int),
|
||||
void *private_data);
|
||||
|
||||
/* public host1x sync-point management APIs */
|
||||
#ifdef CONFIG_TEGRA_HOST1X
|
||||
|
||||
static inline struct flcn *get_flcn(struct platform_device *pdev)
|
||||
{
|
||||
struct nvhost_device_data *pdata = platform_get_drvdata(pdev);
|
||||
|
||||
return pdata ? pdata->falcon_data : NULL;
|
||||
}
|
||||
|
||||
static inline int nvhost_module_set_rate(struct platform_device *dev, void *priv,
|
||||
unsigned long constraint, int index,
|
||||
unsigned long attr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int nvhost_module_add_client(struct platform_device *dev, void *priv)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void nvhost_module_remove_client(struct platform_device *dev, void *priv) { }
|
||||
|
||||
static inline int nvhost_syncpt_get_cv_dev_address_table(struct platform_device *engine_pdev,
|
||||
int *count, dma_addr_t **table)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline const struct firmware *
|
||||
nvhost_client_request_firmware(struct platform_device *dev,
|
||||
const char *fw_name, bool warn)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void nvhost_debug_dump_device(struct platform_device *pdev)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int nvhost_fence_create_fd(
|
||||
struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts,
|
||||
const char *name,
|
||||
s32 *fence_fd)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int nvhost_fence_foreach_pt(
|
||||
struct nvhost_fence *fence,
|
||||
int (*iter)(struct nvhost_ctrl_sync_fence_info, void *),
|
||||
void *data)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline struct nvhost_job *nvhost_job_alloc(struct nvhost_channel *ch,
|
||||
int num_cmdbufs, int num_relocs, int num_waitchks,
|
||||
int num_syncpts)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void nvhost_job_put(struct nvhost_job *job) {}
|
||||
|
||||
static inline int nvhost_job_add_client_gather_address(struct nvhost_job *job,
|
||||
u32 num_words, u32 class_id, dma_addr_t gather_address)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int nvhost_channel_map(struct nvhost_device_data *pdata,
|
||||
struct nvhost_channel **ch,
|
||||
void *identifier)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int nvhost_channel_submit(struct nvhost_job *job)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline void nvhost_putchannel(struct nvhost_channel *ch, int cnt) {}
|
||||
|
||||
static inline struct nvhost_fence *nvhost_fence_get(int fd)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void nvhost_fence_put(struct nvhost_fence *fence) {}
|
||||
|
||||
static inline int nvhost_fence_num_pts(struct nvhost_fence *fence)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline dma_addr_t nvhost_t194_get_reloc_phys_addr(dma_addr_t phys_addr,
|
||||
u32 reloc_type)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline dma_addr_t nvhost_t23x_get_reloc_phys_addr(dma_addr_t phys_addr,
|
||||
u32 reloc_type)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void nvhost_eventlib_log_task(struct platform_device *pdev,
|
||||
u32 syncpt_id,
|
||||
u32 syncpt_thres,
|
||||
u64 timestamp_start,
|
||||
u64 timestamp_end)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void nvhost_eventlib_log_submit(struct platform_device *pdev,
|
||||
u32 syncpt_id,
|
||||
u32 syncpt_thresh,
|
||||
u64 timestamp)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void nvhost_eventlib_log_fences(struct platform_device *pdev,
|
||||
u32 task_syncpt_id,
|
||||
u32 task_syncpt_thresh,
|
||||
struct nvdev_fence *fences,
|
||||
u8 num_fences,
|
||||
u32 kind,
|
||||
u64 timestamp)
|
||||
{
|
||||
}
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
void nvhost_register_dump_device(
|
||||
struct platform_device *dev,
|
||||
void (*nvgpu_debug_dump_device)(void *),
|
||||
void *data);
|
||||
void nvhost_unregister_dump_device(struct platform_device *dev);
|
||||
#else
|
||||
static inline void nvhost_register_dump_device(
|
||||
struct platform_device *dev,
|
||||
void (*nvgpu_debug_dump_device)(void *),
|
||||
void *data)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void nvhost_unregister_dump_device(struct platform_device *dev)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
void host1x_channel_writel(struct nvhost_channel *ch, u32 r, u32 v);
|
||||
u32 host1x_channel_readl(struct nvhost_channel *ch, u32 r);
|
||||
|
||||
void host1x_sync_writel(struct nvhost_master *dev, u32 r, u32 v);
|
||||
u32 host1x_sync_readl(struct nvhost_master *dev, u32 r);
|
||||
|
||||
/* public host1x power management APIs */
|
||||
bool nvhost_module_powered_ext(struct platform_device *dev);
|
||||
/* This power ON only host1x and doesn't power ON module */
|
||||
int nvhost_module_busy_ext(struct platform_device *dev);
|
||||
/* This power OFF only host1x and doesn't power OFF module */
|
||||
void nvhost_module_idle_ext(struct platform_device *dev);
|
||||
|
||||
/* public api to return platform_device ptr to the default host1x instance */
|
||||
struct platform_device *nvhost_get_default_device(void);
|
||||
|
||||
/* Public PM nvhost APIs. */
|
||||
/* This power ON both host1x and module */
|
||||
int nvhost_module_busy(struct platform_device *dev);
|
||||
/* This power OFF both host1x and module */
|
||||
void nvhost_module_idle(struct platform_device *dev);
|
||||
|
||||
/* public api to register/unregister a subdomain */
|
||||
void nvhost_register_client_domain(struct generic_pm_domain *domain);
|
||||
void nvhost_unregister_client_domain(struct generic_pm_domain *domain);
|
||||
|
||||
int nvhost_module_add_client(struct platform_device *dev,
|
||||
void *priv);
|
||||
void nvhost_module_remove_client(struct platform_device *dev,
|
||||
void *priv);
|
||||
|
||||
int nvhost_module_set_rate(struct platform_device *dev, void *priv,
|
||||
unsigned long constraint, int index, unsigned long attr);
|
||||
|
||||
/* public APIs required to submit in-kernel work */
|
||||
int nvhost_channel_map(struct nvhost_device_data *pdata,
|
||||
struct nvhost_channel **ch,
|
||||
void *identifier);
|
||||
void nvhost_putchannel(struct nvhost_channel *ch, int cnt);
|
||||
/* Allocate memory for a job. Just enough memory will be allocated to
|
||||
* accomodate the submit announced in submit header.
|
||||
*/
|
||||
struct nvhost_job *nvhost_job_alloc(struct nvhost_channel *ch,
|
||||
int num_cmdbufs, int num_relocs, int num_waitchks,
|
||||
int num_syncpts);
|
||||
/* Decrement reference job, free if goes to zero. */
|
||||
void nvhost_job_put(struct nvhost_job *job);
|
||||
|
||||
/* Add a gather with IOVA address to job */
|
||||
int nvhost_job_add_client_gather_address(struct nvhost_job *job,
|
||||
u32 num_words, u32 class_id, dma_addr_t gather_address);
|
||||
int nvhost_channel_submit(struct nvhost_job *job);
|
||||
|
||||
/* public host1x sync-point management APIs */
|
||||
u32 nvhost_get_syncpt_client_managed(struct platform_device *pdev,
|
||||
const char *syncpt_name);
|
||||
void nvhost_syncpt_get_ref_ext(struct platform_device *pdev, u32 id);
|
||||
const char *nvhost_syncpt_get_name(struct platform_device *dev, int id);
|
||||
void nvhost_syncpt_cpu_incr_ext(struct platform_device *dev, u32 id);
|
||||
int nvhost_syncpt_read_ext_check(struct platform_device *dev, u32 id, u32 *val);
|
||||
int nvhost_syncpt_wait_timeout_ext(struct platform_device *dev, u32 id, u32 thresh,
|
||||
u32 timeout, u32 *value, struct timespec64 *ts);
|
||||
int nvhost_syncpt_create_fence_single_ext(struct platform_device *dev,
|
||||
u32 id, u32 thresh, const char *name, int *fence_fd);
|
||||
void nvhost_syncpt_set_min_eq_max_ext(struct platform_device *dev, u32 id);
|
||||
int nvhost_syncpt_nb_pts_ext(struct platform_device *dev);
|
||||
bool nvhost_syncpt_is_valid_pt_ext(struct platform_device *dev, u32 id);
|
||||
u32 nvhost_syncpt_read_minval(struct platform_device *dev, u32 id);
|
||||
void nvhost_syncpt_set_maxval(struct platform_device *dev, u32 id, u32 val);
|
||||
int nvhost_syncpt_fd_get_ext(int fd, struct platform_device *pdev, u32 *id);
|
||||
|
||||
void nvhost_eventlib_log_task(struct platform_device *pdev,
|
||||
u32 syncpt_id,
|
||||
u32 syncpt_thres,
|
||||
u64 timestamp_start,
|
||||
u64 timestamp_end);
|
||||
|
||||
void nvhost_eventlib_log_submit(struct platform_device *pdev,
|
||||
u32 syncpt_id,
|
||||
u32 syncpt_thresh,
|
||||
u64 timestamp);
|
||||
|
||||
void nvhost_eventlib_log_fences(struct platform_device *pdev,
|
||||
u32 task_syncpt_id,
|
||||
u32 task_syncpt_thresh,
|
||||
struct nvdev_fence *fences,
|
||||
u8 num_fences,
|
||||
u32 kind,
|
||||
u64 timestamp);
|
||||
|
||||
dma_addr_t nvhost_t194_get_reloc_phys_addr(dma_addr_t phys_addr,
|
||||
u32 reloc_type);
|
||||
dma_addr_t nvhost_t23x_get_reloc_phys_addr(dma_addr_t phys_addr,
|
||||
u32 reloc_type);
|
||||
|
||||
/* public host1x interrupt management APIs */
|
||||
int nvhost_intr_register_fast_notifier(struct platform_device *pdev,
|
||||
u32 id, u32 thresh,
|
||||
void (*callback)(void *, int),
|
||||
void *private_data);
|
||||
|
||||
#if IS_ENABLED(CONFIG_TEGRA_GRHOST) && defined(CONFIG_DEBUG_FS)
|
||||
void nvhost_debug_dump_device(struct platform_device *pdev);
|
||||
#else
|
||||
static inline void nvhost_debug_dump_device(struct platform_device *pdev)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_TEGRA_GRHOST)
|
||||
const struct firmware *
|
||||
nvhost_client_request_firmware(struct platform_device *dev,
|
||||
const char *fw_name, bool warn);
|
||||
#else
|
||||
static inline const struct firmware *
|
||||
nvhost_client_request_firmware(struct platform_device *dev,
|
||||
const char *fw_name, bool warn)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_TEGRA_GRHOST_SYNC)
|
||||
|
||||
int nvhost_fence_foreach_pt(
|
||||
struct nvhost_fence *fence,
|
||||
int (*iter)(struct nvhost_ctrl_sync_fence_info, void *),
|
||||
void *data);
|
||||
|
||||
int nvhost_fence_get_pt(
|
||||
struct nvhost_fence *fence, size_t i,
|
||||
u32 *id, u32 *threshold);
|
||||
|
||||
struct nvhost_fence *nvhost_fence_create(
|
||||
struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts,
|
||||
const char *name);
|
||||
int nvhost_fence_create_fd(
|
||||
struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts,
|
||||
const char *name,
|
||||
s32 *fence_fd);
|
||||
|
||||
struct nvhost_fence *nvhost_fence_get(int fd);
|
||||
struct nvhost_fence *nvhost_fence_dup(struct nvhost_fence *fence);
|
||||
int nvhost_fence_num_pts(struct nvhost_fence *fence);
|
||||
int nvhost_fence_install(struct nvhost_fence *fence, int fence_fd);
|
||||
void nvhost_fence_put(struct nvhost_fence *fence);
|
||||
void nvhost_fence_wait(struct nvhost_fence *fence, u32 timeout_in_ms);
|
||||
|
||||
#else
|
||||
|
||||
static inline int nvhost_fence_foreach_pt(
|
||||
struct nvhost_fence *fence,
|
||||
int (*iter)(struct nvhost_ctrl_sync_fence_info, void *d),
|
||||
void *d)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline struct nvhost_fence *nvhost_create_fence(
|
||||
struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts,
|
||||
const char *name)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline int nvhost_fence_create_fd(
|
||||
struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts,
|
||||
const char *name,
|
||||
s32 *fence_fd)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline struct nvhost_fence *nvhost_fence_get(int fd)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int nvhost_fence_num_pts(struct nvhost_fence *fence)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void nvhost_fence_put(struct nvhost_fence *fence)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void nvhost_fence_wait(struct nvhost_fence *fence, u32 timeout_in_ms)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_TEGRA_GRHOST_SYNC) && !defined(CONFIG_SYNC)
|
||||
int nvhost_dma_fence_unpack(struct dma_fence *fence, u32 *id, u32 *threshold);
|
||||
bool nvhost_dma_fence_is_waitable(struct dma_fence *fence);
|
||||
#else
|
||||
static inline int nvhost_dma_fence_unpack(struct dma_fence *fence, u32 *id,
|
||||
u32 *threshold)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
static inline bool nvhost_dma_fence_is_waitable(struct dma_fence *fence)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_TEGRA_GRHOST_SYNC) && defined(CONFIG_SYNC)
|
||||
struct sync_fence *nvhost_sync_fdget(int fd);
|
||||
int nvhost_sync_num_pts(struct sync_fence *fence);
|
||||
struct sync_fence *nvhost_sync_create_fence(struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts, const char *name);
|
||||
int nvhost_sync_create_fence_fd(
|
||||
struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts,
|
||||
const char *name,
|
||||
s32 *fence_fd);
|
||||
int nvhost_sync_fence_set_name(int fence_fd, const char *name);
|
||||
u32 nvhost_sync_pt_id(struct sync_pt *__pt);
|
||||
u32 nvhost_sync_pt_thresh(struct sync_pt *__pt);
|
||||
struct sync_pt *nvhost_sync_pt_from_fence_index(struct sync_fence *fence,
|
||||
u32 sync_pt_index);
|
||||
#else
|
||||
static inline struct sync_fence *nvhost_sync_fdget(int fd)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int nvhost_sync_num_pts(struct sync_fence *fence)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline struct sync_fence *nvhost_sync_create_fence(struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts, const char *name)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline int nvhost_sync_create_fence_fd(
|
||||
struct platform_device *pdev,
|
||||
struct nvhost_ctrl_sync_fence_info *pts,
|
||||
u32 num_pts,
|
||||
const char *name,
|
||||
s32 *fence_fd)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int nvhost_sync_fence_set_name(int fence_fd, const char *name)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_sync_pt_id(struct sync_pt *__pt)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_sync_pt_thresh(struct sync_pt *__pt)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline struct sync_pt *nvhost_sync_pt_from_fence_index(
|
||||
struct sync_fence *fence, u32 sync_pt_index)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Hacky way to get access to struct nvhost_device_data for VI device. */
|
||||
extern struct nvhost_device_data t20_vi_info;
|
||||
extern struct nvhost_device_data t30_vi_info;
|
||||
extern struct nvhost_device_data t11_vi_info;
|
||||
extern struct nvhost_device_data t14_vi_info;
|
||||
|
||||
int nvdec_do_idle(void);
|
||||
int nvdec_do_unidle(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,510 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
*
|
||||
* Header file for Tegra Security Engine
|
||||
*/
|
||||
|
||||
#ifndef _CRYPTO_TEGRA_SE_H
|
||||
#define _CRYPTO_TEGRA_SE_H
|
||||
|
||||
#include <crypto/hash.h>
|
||||
#include <crypto/sha1.h>
|
||||
|
||||
#define PFX "tegra-se-nvhost: "
|
||||
|
||||
#define ENCRYPT 1
|
||||
#define DECRYPT 0
|
||||
|
||||
#define TEGRA_SE_CRA_PRIORITY 300
|
||||
#define TEGRA_SE_COMPOSITE_PRIORITY 400
|
||||
#define TEGRA_SE_CRYPTO_QUEUE_LENGTH 100
|
||||
#define SE_MAX_SRC_SG_COUNT 50
|
||||
#define SE_MAX_DST_SG_COUNT 50
|
||||
|
||||
#define TEGRA_SE_KEYSLOT_COUNT 16
|
||||
#define SE_MAX_LAST_BLOCK_SIZE 0xFFFFF
|
||||
|
||||
/* SE register definitions */
|
||||
#define SE1_AES0_CONFIG_REG_OFFSET 0x204
|
||||
#define SE2_AES1_CONFIG_REG_OFFSET 0x404
|
||||
|
||||
#define SE_AES_CRYPTO_CONFIG_OFFSET 0x4
|
||||
#define SE_AES_IN_ADDR_OFFSET 0x8
|
||||
#define SE_AES_IN_ADDR_HI_OFFSET 0xC
|
||||
#define SE_AES_OUT_ADDR_OFFSET 0x10
|
||||
#define SE_AES_OUT_ADDR_HI_OFFSET 0x14
|
||||
#define SE_AES_CRYPTO_LINEAR_CTR 0x18
|
||||
#define SE_AES_CRYPTO_LAST_BLOCK_OFFSET 0x28
|
||||
#define SE_AES_OPERATION_OFFSET 0x34
|
||||
#define SE_AES_CRYPTO_KEYTABLE_ADDR_OFFSET 0xB8
|
||||
#define SE_AES_CRYPTO_KEYTABLE_DATA_OFFSET 0xBC
|
||||
#define SE_AES_CRYPTO_CTR_SPARE 0xE0
|
||||
#define SE_AES_CTR_LITTLE_ENDIAN 1
|
||||
|
||||
#define SE_CONFIG_ENC_ALG_SHIFT 12
|
||||
#define SE_CONFIG_DEC_ALG_SHIFT 8
|
||||
#define ALG_AES_ENC 1
|
||||
#define ALG_RNG 2
|
||||
#define ALG_SHA 3
|
||||
#define ALG_RSA 4
|
||||
#define ALG_NOP 0
|
||||
#define ALG_AES_DEC 1
|
||||
#define ALG_KEYFETCH 5
|
||||
#define ALG_HMAC 7
|
||||
#define ALG_KDF 8
|
||||
#define ALG_INS 13
|
||||
#define SE_CONFIG_ENC_ALG(x) (x << SE_CONFIG_ENC_ALG_SHIFT)
|
||||
#define SE_CONFIG_DEC_ALG(x) (x << SE_CONFIG_DEC_ALG_SHIFT)
|
||||
#define SE_CONFIG_DST_SHIFT 2
|
||||
#define DST_MEMORY 0
|
||||
#define DST_HASHREG 1
|
||||
#define DST_KEYTAB 2
|
||||
#define DST_SRK 3
|
||||
#define DST_RSAREG 4
|
||||
#define SE_CONFIG_DST(x) (x << SE_CONFIG_DST_SHIFT)
|
||||
#define SE_CONFIG_ENC_MODE_SHIFT 24
|
||||
#define SE_CONFIG_DEC_MODE_SHIFT 16
|
||||
#define MODE_KEY128 0
|
||||
#define MODE_KEY192 1
|
||||
#define MODE_KEY256 2
|
||||
#define MODE_GMAC 3
|
||||
#define MODE_GCM 4
|
||||
#define MODE_GCM_FINAL 5
|
||||
#define MODE_CMAC 7
|
||||
|
||||
#define MODE_SHA1 0
|
||||
#define MODE_SHA224 4
|
||||
#define MODE_SHA256 5
|
||||
#define MODE_SHA384 6
|
||||
#define MODE_SHA512 7
|
||||
#define MODE_SHA3_224 9
|
||||
#define MODE_SHA3_256 10
|
||||
#define MODE_SHA3_384 11
|
||||
#define MODE_SHA3_512 12
|
||||
#define MODE_SHAKE128 13
|
||||
#define MODE_SHAKE256 14
|
||||
#define MODE_HMAC_SHA256_1KEY 0
|
||||
#define MODE_HMAC_SHA256_2KEY 1
|
||||
#define SE_CONFIG_ENC_MODE(x) (x << SE_CONFIG_ENC_MODE_SHIFT)
|
||||
#define SE_CONFIG_DEC_MODE(x) (x << SE_CONFIG_DEC_MODE_SHIFT)
|
||||
|
||||
#define SE_RNG_CONFIG_REG_OFFSET 0x234
|
||||
#define DRBG_MODE_SHIFT 0
|
||||
#define DRBG_MODE_NORMAL 0
|
||||
#define DRBG_MODE_FORCE_INSTANTION 1
|
||||
#define DRBG_MODE_FORCE_RESEED 2
|
||||
#define SE_RNG_CONFIG_MODE(x) (x << DRBG_MODE_SHIFT)
|
||||
|
||||
#define SE_RNG_SRC_CONFIG_REG_OFFSET 0x2d8
|
||||
#define DRBG_RO_ENT_SRC_SHIFT 1
|
||||
#define DRBG_RO_ENT_SRC_ENABLE 1
|
||||
#define DRBG_RO_ENT_SRC_DISABLE 0
|
||||
#define SE_RNG_SRC_CONFIG_RO_ENT_SRC(x) (x << DRBG_RO_ENT_SRC_SHIFT)
|
||||
#define DRBG_RO_ENT_SRC_LOCK_SHIFT 0
|
||||
#define DRBG_RO_ENT_SRC_LOCK_ENABLE 1
|
||||
#define DRBG_RO_ENT_SRC_LOCK_DISABLE 0
|
||||
#define SE_RNG_SRC_CONFIG_RO_ENT_SRC_LOCK(x) (x << DRBG_RO_ENT_SRC_LOCK_SHIFT)
|
||||
|
||||
#define DRBG_SRC_SHIFT 2
|
||||
#define DRBG_SRC_NONE 0
|
||||
#define DRBG_SRC_ENTROPY 1
|
||||
#define DRBG_SRC_LFSR 2
|
||||
#define SE_RNG_CONFIG_SRC(x) (x << DRBG_SRC_SHIFT)
|
||||
|
||||
#define SE_RNG_RESEED_INTERVAL_REG_OFFSET 0x2dc
|
||||
|
||||
#define SE_KEYTABLE_REG_OFFSET 0x31c
|
||||
#define SE_CRYPTO_KEYIV_PKT_SUBKEY_SEL_SHIFT 3
|
||||
#define SE_CRYPTO_KEYIV_PKT_SUBKEY_SEL(x) \
|
||||
(x << SE_CRYPTO_KEYIV_PKT_SUBKEY_SEL_SHIFT)
|
||||
#define SUBKEY_SEL_KEY1 0
|
||||
#define SUBKEY_SEL_KEY2 1
|
||||
#define SE_KEYTABLE_SLOT_SHIFT 4
|
||||
#define SE_KEYTABLE_SLOT(x) (x << SE_KEYTABLE_SLOT_SHIFT)
|
||||
#define SE_KEYTABLE_QUAD_SHIFT 2
|
||||
#define QUAD_KEYS_128 0
|
||||
#define QUAD_KEYS_192 1
|
||||
#define QUAD_KEYS_256 1
|
||||
#define QUAD_ORG_IV 2
|
||||
#define QUAD_UPDTD_IV 3
|
||||
#define SE_KEYTABLE_QUAD(x) (x << SE_KEYTABLE_QUAD_SHIFT)
|
||||
#define SE_KEYTABLE_OP_TYPE_SHIFT 9
|
||||
#define OP_READ 0
|
||||
#define OP_WRITE 1
|
||||
#define SE_KEYTABLE_OP_TYPE(x) (x << SE_KEYTABLE_OP_TYPE_SHIFT)
|
||||
#define SE_KEYTABLE_TABLE_SEL_SHIFT 8
|
||||
#define TABLE_KEYIV 0
|
||||
#define TABLE_SCHEDULE 1
|
||||
#define SE_KEYTABLE_TABLE_SEL(x) (x << SE_KEYTABLE_TABLE_SEL_SHIFT)
|
||||
#define SE_KEYTABLE_PKT_SHIFT 0
|
||||
#define SE_KEYTABLE_PKT(x) (x << SE_KEYTABLE_PKT_SHIFT)
|
||||
|
||||
#define SE_OP_DONE_SHIFT 4
|
||||
#define OP_DONE 1
|
||||
#define SE_OP_DONE(x, y) ((x) && (y << SE_OP_DONE_SHIFT))
|
||||
|
||||
#define SE_CRYPTO_HASH_SHIFT 0
|
||||
#define HASH_DISABLE 0
|
||||
#define HASH_ENABLE 1
|
||||
#define SE_CRYPTO_HASH(x) (x << SE_CRYPTO_HASH_SHIFT)
|
||||
|
||||
#define SE4_SHA_IN_ADDR_OFFSET 0x8
|
||||
#define SE4_SHA_TASK_CONFIG 0x108
|
||||
#define HW_INIT_HASH_DISABLE 0
|
||||
#define HW_INIT_HASH_ENABLE 1
|
||||
#define SE4_HW_INIT_HASH_SHIFT 0
|
||||
#define SE4_HW_INIT_HASH(x) (x << SE4_HW_INIT_HASH_SHIFT)
|
||||
|
||||
#define SE_CRYPTO_XOR_POS_SHIFT 1
|
||||
#define XOR_BYPASS 0
|
||||
#define XOR_BOTH 1
|
||||
#define XOR_TOP 2
|
||||
#define XOR_BOTTOM 3
|
||||
#define SE_CRYPTO_XOR_POS(x) (x << SE_CRYPTO_XOR_POS_SHIFT)
|
||||
#define SE_CRYPTO_INPUT_SEL_SHIFT 3
|
||||
#define INPUT_MEMORY 0
|
||||
#define INPUT_RANDOM 1
|
||||
#define INPUT_AESOUT 2
|
||||
#define INPUT_LNR_CTR 3
|
||||
#define SE_CRYPTO_INPUT_SEL(x) (x << SE_CRYPTO_INPUT_SEL_SHIFT)
|
||||
#define SE_CRYPTO_VCTRAM_SEL_SHIFT 5
|
||||
#define VCTRAM_MEMORY 0
|
||||
#define VCTRAM_TWEAK 1
|
||||
#define VCTRAM_AESOUT 2
|
||||
#define VCTRAM_PREVAHB 3
|
||||
#define SE_CRYPTO_VCTRAM_SEL(x) (x << SE_CRYPTO_VCTRAM_SEL_SHIFT)
|
||||
#define SE_CRYPTO_IV_SEL_SHIFT 7
|
||||
#define IV_ORIGINAL 0
|
||||
#define IV_UPDATED 1
|
||||
#define IV_REG 2
|
||||
#define SE_CRYPTO_IV_SEL(x) (x << SE_CRYPTO_IV_SEL_SHIFT)
|
||||
#define SE_CRYPTO_CORE_SEL_SHIFT 9
|
||||
#define CORE_DECRYPT 0
|
||||
#define CORE_ENCRYPT 1
|
||||
#define SE_CRYPTO_CORE_SEL(x) (x << SE_CRYPTO_CORE_SEL_SHIFT)
|
||||
#define SE_CRYPTO_KEY2_INDEX_SHIFT 28
|
||||
#define SE_CRYPTO_KEY2_INDEX(x) (x << SE_CRYPTO_KEY2_INDEX_SHIFT)
|
||||
#define SE_CRYPTO_KEY_INDEX_SHIFT 24
|
||||
#define SE_CRYPTO_KEY_INDEX(x) (x << SE_CRYPTO_KEY_INDEX_SHIFT)
|
||||
#define SE_CRYPTO_CTR_CNTN_SHIFT 11
|
||||
#define SE_CRYPTO_CTR_CNTN(x) (x << SE_CRYPTO_CTR_CNTN_SHIFT)
|
||||
|
||||
#define SE_CRYPTO_CTR_REG_COUNT 4
|
||||
|
||||
#define OP_START 1
|
||||
#define OP_RESTART_OUT 2
|
||||
#define OP_CTX_SAVE 3
|
||||
#define OP_RESTART_IN 4
|
||||
#define OP_RESTART_INOUT 5
|
||||
#define OP_DUMMY 6
|
||||
#define SE_OPERATION_OP_SHIFT 0
|
||||
#define SE_OPERATION_OP(x) (x << SE_OPERATION_OP_SHIFT)
|
||||
|
||||
#define SE_OPERATION_LASTBUF_SHIFT 16
|
||||
#define SE_OPERATION_LASTBUF(x) (x << SE_OPERATION_LASTBUF_SHIFT)
|
||||
#define LASTBUF_TRUE 1
|
||||
#define LASTBUF_FALSE 0
|
||||
|
||||
#define SE_OPERATION_WRSTALL_SHIFT 15
|
||||
#define SE_OPERATION_WRSTALL(x) (x << SE_OPERATION_WRSTALL_SHIFT)
|
||||
#define WRSTALL_TRUE 1
|
||||
#define WRSTALL_FALSE 0
|
||||
|
||||
#define SE_OPERATION_FINAL_SHIFT 5
|
||||
#define SE_OPERATION_FINAL(x) (x << SE_OPERATION_FINAL_SHIFT)
|
||||
#define FINAL_TRUE 1
|
||||
#define FINAL_FALSE 0
|
||||
|
||||
#define SE_OPERATION_INIT_SHIFT 4
|
||||
#define SE_OPERATION_INIT(x) (x << SE_OPERATION_INIT_SHIFT)
|
||||
#define INIT_TRUE 1
|
||||
#define INIT_FALSE 0
|
||||
|
||||
#define SE_ADDR_HI_MSB_SHIFT 24
|
||||
#define SE_ADDR_HI_SZ_SHIFT 0
|
||||
#define SE_ADDR_HI_MSB(x) (x << SE_ADDR_HI_MSB_SHIFT)
|
||||
#define MSB(x) ((x & 0xFF00000000) >> 32)
|
||||
#define SE_ADDR_HI_SZ(x) (x << SE_ADDR_HI_SZ_SHIFT)
|
||||
|
||||
#define SE_LAST_BLOCK_RESIDUAL_BITS_SHIFT 20
|
||||
#define SE_LAST_BLOCK_RESIDUAL_BITS(x) (x << SE_LAST_BLOCK_RESIDUAL_BITS_SHIFT)
|
||||
|
||||
#define SE_BUFF_SIZE_MASK 0xFF000000
|
||||
|
||||
#define SE_MAX_TASKS_PER_SUBMIT 64
|
||||
#define SE_MAX_SUBMIT_CHAIN_SZ 10
|
||||
#define SE_WORD_SIZE_BYTES 4
|
||||
|
||||
#define SE_MAX_MEM_ALLOC 4194304
|
||||
#define SE_MAX_GATHER_BUF_SZ 32768
|
||||
#define SE_MAX_AESBUF_ALLOC (SE_MAX_MEM_ALLOC / SE_MAX_GATHER_BUF_SZ)
|
||||
#define SE_MAX_AESBUF_TIMEOUT (20 * SE_MAX_AESBUF_ALLOC)
|
||||
|
||||
/* FIXME: The below 2 macros should fine tuned
|
||||
* based on discussions with CPU team
|
||||
*/
|
||||
#define SE_MAX_CMDBUF_TIMEOUT (200 * SE_MAX_SUBMIT_CHAIN_SZ)
|
||||
#define SE_WAIT_UDELAY 500 /* micro seconds */
|
||||
|
||||
#define SE_KEYSLOT_TIMEOUT 100
|
||||
#define SE_KEYSLOT_MDELAY 1000
|
||||
|
||||
#define SE_INT_ENABLE_REG_OFFSET 0x88
|
||||
#define SE1_INT_ENABLE_SHIFT 1
|
||||
#define SE1_INT_ENABLE(x) (x << SE1_INT_ENABLE_SHIFT)
|
||||
#define SE2_INT_ENABLE_SHIFT 0
|
||||
#define SE2_INT_ENABLE(x) (x << SE2_INT_ENABLE_SHIFT)
|
||||
#define SE3_INT_ENABLE_SHIFT 2
|
||||
#define SE3_INT_ENABLE(x) (x << SE3_INT_ENABLE_SHIFT)
|
||||
#define SE4_INT_ENABLE_SHIFT 3
|
||||
#define SE4_INT_ENABLE(x) (x << SE4_INT_ENABLE_SHIFT)
|
||||
|
||||
#define INT_DISABLE 0
|
||||
#define INT_ENABLE 1
|
||||
|
||||
#define SE1_AES0_INT_ENABLE_OFFSET 0x2EC
|
||||
#define SE2_AES1_INT_ENABLE_OFFSET 0x4EC
|
||||
#define SE3_RSA_INT_ENABLE_OFFSET 0x754
|
||||
#define SE4_SHA_INT_ENABLE_OFFSET 0x180
|
||||
|
||||
#define SE1_AES0_INT_STATUS_REG_OFFSET 0x2F0
|
||||
#define SE2_AES1_INT_STATUS_REG_OFFSET 0x4F0
|
||||
#define SE3_RSA_INT_STATUS_REG_OFFSET 0x758
|
||||
#define SE4_SHA_INT_STATUS_REG_OFFSET 0x184
|
||||
|
||||
#define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET 0X330
|
||||
#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT 0
|
||||
#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x) \
|
||||
(x << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT)
|
||||
|
||||
#define SE_KEYTABLE_QUAD_SIZE_BYTES 16
|
||||
|
||||
#define SE_SPARE_0_REG_OFFSET 0x80c
|
||||
|
||||
#define TEGRA_SE_SHA_MAX_BLOCK_SIZE 128
|
||||
|
||||
#define SE4_SHA_CONFIG_REG_OFFSET 0x104
|
||||
#define SE_SHA_MSG_LENGTH_OFFSET 0x18
|
||||
#define SE_SHA_OPERATION_OFFSET 0x78
|
||||
#define SE_SHA_HASH_LENGTH 0xa8
|
||||
|
||||
#define SHA_DISABLE 0
|
||||
#define SHA_ENABLE 1
|
||||
|
||||
#define SE_HASH_RESULT_REG_OFFSET 0x13c
|
||||
#define SE_CMAC_RESULT_REG_OFFSET 0x4c4
|
||||
#define T234_SE_CMAC_RESULT_REG_OFFSET 0x0c0
|
||||
|
||||
#define SE_STATIC_MEM_ALLOC_BUFSZ 512
|
||||
|
||||
#define TEGRA_SE_KEY_256_SIZE 32
|
||||
#define TEGRA_SE_KEY_512_SIZE 64
|
||||
#define TEGRA_SE_KEY_192_SIZE 24
|
||||
#define TEGRA_SE_KEY_128_SIZE 16
|
||||
#define TEGRA_SE_AES_BLOCK_SIZE 16
|
||||
#define TEGRA_SE_AES_MIN_KEY_SIZE 16
|
||||
#define TEGRA_SE_AES_MAX_KEY_SIZE 64
|
||||
#define TEGRA_SE_AES_IV_SIZE 16
|
||||
#define TEGRA_SE_RNG_IV_SIZE 16
|
||||
#define TEGRA_SE_RNG_DT_SIZE 16
|
||||
#define TEGRA_SE_RNG_KEY_SIZE 16
|
||||
#define TEGRA_SE_RNG_SEED_SIZE (TEGRA_SE_RNG_IV_SIZE + \
|
||||
TEGRA_SE_RNG_KEY_SIZE + \
|
||||
TEGRA_SE_RNG_DT_SIZE)
|
||||
#define TEGRA_SE_AES_CMAC_DIGEST_SIZE 16
|
||||
#define TEGRA_SE_AES_CBC_MAC_DIGEST_SIZE 16
|
||||
#define TEGRA_SE_RSA512_INPUT_SIZE 64
|
||||
#define TEGRA_SE_RSA1024_INPUT_SIZE 128
|
||||
#define TEGRA_SE_RSA1536_INPUT_SIZE 192
|
||||
#define TEGRA_SE_RSA2048_INPUT_SIZE 256
|
||||
|
||||
#define TEGRA_SE_AES_CMAC_STATE_SIZE 16
|
||||
#define SHA1_STATE_SIZE 20
|
||||
#define SHA224_STATE_SIZE 32
|
||||
#define SHA256_STATE_SIZE 32
|
||||
#define SHA384_STATE_SIZE 64
|
||||
#define SHA512_STATE_SIZE 64
|
||||
#define SHA3_224_STATE_SIZE 200
|
||||
#define SHA3_256_STATE_SIZE 200
|
||||
#define SHA3_384_STATE_SIZE 200
|
||||
#define SHA3_512_STATE_SIZE 200
|
||||
|
||||
#define TEGRA_SE_RSA_KEYSLOT_COUNT 4
|
||||
#define SE_RSA_OUTPUT 0x628
|
||||
|
||||
#define RSA_KEY_SLOT_ONE 0
|
||||
#define RSA_KEY_SLOT_TW0 1
|
||||
#define RSA_KEY_SLOT_THREE 2
|
||||
#define RSA_KEY_SLOT_FOUR 3
|
||||
#define RSA_KEY_NUM_SHIFT 7
|
||||
#define RSA_KEY_NUM(x) (x << RSA_KEY_NUM_SHIFT)
|
||||
|
||||
#define RSA_KEY_TYPE_EXP 0
|
||||
#define RSA_KEY_TYPE_MOD 1
|
||||
#define RSA_KEY_TYPE_SHIFT 6
|
||||
#define RSA_KEY_TYPE(x) (x << RSA_KEY_TYPE_SHIFT)
|
||||
|
||||
#define RSA_KEY_SLOT_SHIFT 23
|
||||
#define RSA_KEY_SLOT(x) (x << RSA_KEY_SLOT_SHIFT)
|
||||
|
||||
#define SE3_RSA_CONFIG_REG_OFFSET 0x604
|
||||
#define SE_RSA_OPERATION_OFFSET 0x20
|
||||
#define SE_RSA_KEYTABLE_ADDR_OFFSET 0x148
|
||||
#define SE_RSA_KEYTABLE_DATA_OFFSET 0x14C
|
||||
|
||||
#define RSA_KEY_PKT_WORD_ADDR_SHIFT 0
|
||||
#define RSA_KEY_PKT_WORD_ADDR(x) (x << RSA_KEY_PKT_WORD_ADDR_SHIFT)
|
||||
|
||||
#define SE_RSA_KEYTABLE_PKT_SHIFT 0
|
||||
#define SE_RSA_KEYTABLE_PKT(x) (x << SE_RSA_KEYTABLE_PKT_SHIFT)
|
||||
|
||||
#define SE_MAGIC_PATTERN 0x4E56
|
||||
#define SE_STORE_KEY_IN_MEM 0x0001
|
||||
#define SE_SLOT_NUM_MASK 0xF000
|
||||
#define SE_SLOT_POSITION 12
|
||||
#define SE_KEY_LEN_MASK 0x3FF
|
||||
#define SE_MAGIC_PATTERN_OFFSET 16
|
||||
#define SE_STREAMID_REG_OFFSET 0x90
|
||||
|
||||
#define SE_AES_CRYPTO_AAD_LENGTH_0_OFFSET 0x128
|
||||
#define SE_AES_CRYPTO_MSG_LENGTH_0_OFFSET 0x130
|
||||
|
||||
#define SE_AES_GCM_GMAC_SIZE 16
|
||||
|
||||
/* Key manifest */
|
||||
#define SE_KEYMANIFEST_ORIGIN(x) (x << 0)
|
||||
|
||||
#define SE_KEYMANIFEST_USER(x) (x << 4)
|
||||
#define NS 3
|
||||
|
||||
#define SE_KEYMANIFEST_PURPOSE(x) (x << 8)
|
||||
#define ENC 0
|
||||
#define CMAC 1
|
||||
#define HMAC 2
|
||||
#define KW 3
|
||||
#define KUW 4
|
||||
#define KWUW 5
|
||||
#define KDK 6
|
||||
#define KDD 7
|
||||
#define KDD_KUW 8
|
||||
#define XTS 9
|
||||
#define GCM 10
|
||||
|
||||
#define SE_KEYMANIFEST_SIZE(x) (x << 14)
|
||||
#define KEY128 0
|
||||
#define KEY192 1
|
||||
#define KEY256 2
|
||||
|
||||
#define SE_KEYMANIFEST_EX(x) (x << 12)
|
||||
|
||||
#define SE_AES_CRYPTO_KEYTABLE_KEYMANIFEST_OFFSET 0x110
|
||||
|
||||
#define SE_AES_CRYPTO_KEYTABLE_DST_OFFSET 0x2c
|
||||
|
||||
#define SE_AES_KEY_INDEX(x) (x << 8)
|
||||
|
||||
#define SE_SHA_CRYPTO_KEYTABLE_KEYMANIFEST_OFFSET 0x98
|
||||
#define SE_SHA_CRYPTO_KEYTABLE_DST_OFFSET 0xa4
|
||||
#define SE_SHA_CRYPTO_KEYTABLE_ADDR_OFFSET 0x90
|
||||
#define SE_SHA_CRYPTO_KEYTABLE_DATA_OFFSET 0x94
|
||||
|
||||
/* cdma opcodes */
|
||||
#if 0
|
||||
static inline u32 nvhost_opcode_setclass(
|
||||
unsigned class_id, unsigned offset, unsigned mask)
|
||||
{
|
||||
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_nonincr(unsigned offset, unsigned count)
|
||||
{
|
||||
return (2 << 28) | (offset << 16) | count;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_mask(unsigned offset, unsigned mask)
|
||||
{
|
||||
return (3 << 28) | (offset << 16) | mask;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_imm(unsigned offset, unsigned value)
|
||||
{
|
||||
return (4 << 28) | (offset << 16) | value;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_restart(unsigned address)
|
||||
{
|
||||
return (5 << 28) | (address >> 4);
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_gather_nonincr(unsigned offset, unsigned count)
|
||||
{
|
||||
return (6 << 28) | (offset << 16) | BIT(15) | count;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_gather_incr(unsigned offset, unsigned count)
|
||||
{
|
||||
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_gather_insert(unsigned offset, unsigned incr,
|
||||
unsigned count)
|
||||
{
|
||||
return (6 << 28) | (offset << 16) | BIT(15) | (incr << 14) | count;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_setstreamid(unsigned streamid)
|
||||
{
|
||||
return (7 << 28) | streamid;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_setpayload(unsigned payload)
|
||||
{
|
||||
return (9 << 28) | payload;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_incr_w(unsigned int offset)
|
||||
{
|
||||
/* 20-bit offset supported */
|
||||
return (10 << 28) | offset;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_nonincr_w(unsigned int offset)
|
||||
{
|
||||
/* 20-bit offset supported */
|
||||
return (11 << 28) | offset;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_acquire_mlock(unsigned id)
|
||||
{
|
||||
return (14 << 28) | id;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_opcode_release_mlock(unsigned id)
|
||||
{
|
||||
return (14 << 28) | (1 << 24) | id;
|
||||
}
|
||||
|
||||
static inline u32 nvhost_class_host_incr_syncpt_base(
|
||||
unsigned base_indx, unsigned offset)
|
||||
{
|
||||
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
|
||||
| host1x_uclass_incr_syncpt_base_offset_f(offset);
|
||||
}
|
||||
|
||||
static inline u32 nvhost_class_host_incr_syncpt(
|
||||
unsigned cond, unsigned indx)
|
||||
{
|
||||
return host1x_uclass_incr_syncpt_cond_f(cond)
|
||||
| host1x_uclass_incr_syncpt_indx_f(indx);
|
||||
}
|
||||
|
||||
#define NVHOST_OPCODE_NOOP nvhost_opcode_nonincr(0, 0)
|
||||
|
||||
static inline u32 nvhost_mask2(unsigned x, unsigned y)
|
||||
{
|
||||
return 1 | (1 << (y - x));
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CRYPTO_TEGRA_SE_H */
|
||||
Reference in New Issue
Block a user