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pva: drivers: prevent program of scr regs for gen3

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Since power management is not supported on pre-
silicon platforms on GEN3 avoid programming
registers with lock bit enabled.
Bug 4500579

Signed-off-by: Krish Agarwal <krisha@nvidia.com>
Change-Id: Id4c2352d32a38e3e3408e54e38df3d5f723a4d20
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3077879
Reviewed-by: Sreehari Mohan <sreeharim@nvidia.com>
Reviewed-by: Amruta Sai Anusha Bhamidipati <abhamidipati@nvidia.com>
Reviewed-by: Omar Nemri <onemri@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Krish Agarwal
2024-02-15 07:39:34 -08:00
committed by mobile promotions
parent 5676a53a5b
commit 2664f7f2b7
1 changed files with 3 additions and 6 deletions
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9
drivers/video/tegra/host/pva/pva.c
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@@ -382,16 +382,13 @@ static int pva_init_fw(struct platform_device *pdev)
cfg_priv_ar1_usegreg_r(pva->version), cfg_priv_ar1_usegreg_r(pva->version),
PVA_EXTRACT64((useg_addr), 39, 32, u32)); PVA_EXTRACT64((useg_addr), 39, 32, u32));
if (pdata->version != PVA_HW_GEN1) {
host1x_writel(pdev, evp_scr_r(), PVA_EVP_SCR_VAL | PVA_LOCK_SCR);
host1x_writel(pdev, cfg_scr_priv_0_r(), PVA_PRIV_SCR_VAL | PVA_LOCK_SCR);
host1x_writel(pdev, cfg_scr_ccq_ctrl_r(), PVA_CCQ_SCR_VAL | PVA_LOCK_SCR);
}
/* WAR: Bypass configuring status strl reg due to failure in gen 3 sim test */ /* WAR: Bypass configuring status strl reg due to failure in gen 3 sim test */
if (pdata->version == PVA_HW_GEN2) { if (pdata->version == PVA_HW_GEN2) {
host1x_writel(pdev, cfg_scr_status_ctrl_r(), host1x_writel(pdev, cfg_scr_status_ctrl_r(),
PVA_STATUS_CTL_SCR_VAL | PVA_LOCK_SCR); PVA_STATUS_CTL_SCR_VAL | PVA_LOCK_SCR);
host1x_writel(pdev, evp_scr_r(), PVA_EVP_SCR_VAL | PVA_LOCK_SCR);
host1x_writel(pdev, cfg_scr_priv_0_r(), PVA_PRIV_SCR_VAL | PVA_LOCK_SCR);
host1x_writel(pdev, cfg_scr_ccq_ctrl_r(), PVA_CCQ_SCR_VAL | PVA_LOCK_SCR);
} }
} }