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pinctrl: Add pinctrl driver for Tegra PEX pad controller
Add pinctrl driver for the NVIDIA Tegra pex pad controller. Bug 3621816 Change-Id: I16d05c78882b84819c8911e43899f9cf9400acda Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2704359 GVS: Gerrit_Virtual_Submit
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Laxman Dewangan
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@@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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# Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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obj-m += pinctrl-tegra234-dpaux.o
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obj-m += pinctrl-tegra194-pexclk-padctrl.o
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obj-m += pinctrl-tegra234-dpaux.o
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263
drivers/pinctrl/pinctrl-tegra194-pexclk-padctrl.c
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263
drivers/pinctrl/pinctrl-tegra194-pexclk-padctrl.c
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/slab.h>
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#include <linux/tegra-prod.h>
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#define PCIE_PEXCLK_PADCTL1_REFCLK_OVRD_0 0x8
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#define CFG2TMC_SW_CTL BIT(0)
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enum t194_pexclk_pins {
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T194_PEXCLK_PIN_REFCLK,
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};
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enum t194_pexclk_pinconf_param {
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T194_PEXCLK_SINGLE_ENDED = PIN_CONFIG_END + 1,
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};
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static const struct pinconf_generic_params t194_pexclk_cfg_params[] = {
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{
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.property = "nvidia,pexclk-single-end",
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.param = T194_PEXCLK_SINGLE_ENDED,
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},
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};
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static const struct pinctrl_pin_desc t194_pexclk_pins_desc[] = {
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PINCTRL_PIN(T194_PEXCLK_PIN_REFCLK, "pexclk"),
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};
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struct t194_pexclk_pads {
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const char *name;
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const unsigned int pins[1];
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unsigned int npins;
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};
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static struct t194_pexclk_pads t194_pexclk_pads[] = {
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{
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.name = "pexclk",
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.pins = {
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T194_PEXCLK_PIN_REFCLK,
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},
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.npins = 1,
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},
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};
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struct t194_pexclk_padctrl {
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struct device *dev;
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struct pinctrl_dev *pctl;
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void __iomem *regs[2];
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struct tegra_prod *prod_list;
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struct t194_pexclk_pads *pads;
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int num_pads;
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struct pinctrl_desc pinctrl_desc;
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};
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static int t194_pexclk_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct t194_pexclk_padctrl *pexclk = pinctrl_dev_get_drvdata(pctldev);
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return pexclk->num_pads;
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}
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static const char *t194_pexclk_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group)
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{
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struct t194_pexclk_padctrl *pexclk = pinctrl_dev_get_drvdata(pctldev);
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return pexclk->pads[group].name;
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}
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static int t194_pexclk_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int group,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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struct t194_pexclk_padctrl *pexclk = pinctrl_dev_get_drvdata(pctldev);
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*pins = pexclk->pads[group].pins;
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*num_pins = pexclk->pads[group].npins;
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return 0;
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}
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static const struct pinctrl_ops t194_pexclk_ops = {
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.get_groups_count = t194_pexclk_get_groups_count,
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.get_group_name = t194_pexclk_get_group_name,
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.get_group_pins = t194_pexclk_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinconf_generic_dt_free_map,
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};
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static int t194_pexclk_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int pin,
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unsigned long *config)
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{
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struct t194_pexclk_padctrl *pexclk = pinctrl_dev_get_drvdata(pctldev);
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u16 param = pinconf_to_config_param(*config);
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const struct t194_pexclk_pads *pad = &pexclk->pads[pin];
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u16 arg = 0;
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u32 rval;
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switch (param) {
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case T194_PEXCLK_SINGLE_ENDED:
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rval = readl(pexclk->regs[1] +
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PCIE_PEXCLK_PADCTL1_REFCLK_OVRD_0);
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arg = !!(rval & CFG2TMC_SW_CTL);
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break;
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default:
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dev_dbg(pexclk->dev, "Pin %s does not support param %d\n",
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pad->name, param);
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return -EINVAL;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int t194_pexclk_pinconf_set(struct pinctrl_dev *pctldev,
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unsigned int pin,
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unsigned long *configs,
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unsigned int num_configs)
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{
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struct t194_pexclk_padctrl *pexclk = pinctrl_dev_get_drvdata(pctldev);
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const struct t194_pexclk_pads *pad = &pexclk->pads[pin];
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unsigned int i;
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u32 rval;
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for (i = 0; i < num_configs; i++) {
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u16 param_val = pinconf_to_config_argument(configs[i]);
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u16 param = pinconf_to_config_param(configs[i]);
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switch (param) {
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case T194_PEXCLK_SINGLE_ENDED:
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rval = readl(pexclk->regs[1] +
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PCIE_PEXCLK_PADCTL1_REFCLK_OVRD_0);
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if (param_val)
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rval |= CFG2TMC_SW_CTL;
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else
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rval &= ~CFG2TMC_SW_CTL;
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writel(rval, pexclk->regs[1] +
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PCIE_PEXCLK_PADCTL1_REFCLK_OVRD_0);
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break;
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default:
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dev_err(pexclk->dev, "Pin %s does not support param %d\n",
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pad->name, param);
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return -EINVAL;
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}
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}
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return 0;
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}
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static const struct pinconf_ops t194_pexclk_pinconf_ops = {
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.pin_config_get = t194_pexclk_pinconf_get,
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.pin_config_set = t194_pexclk_pinconf_set,
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.is_generic = true,
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};
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static int t194_pexclk_padctrl_probe(struct platform_device *pdev)
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{
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struct t194_pexclk_padctrl *pexclk;
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struct resource *res;
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int ret, i;
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pexclk = devm_kzalloc(&pdev->dev, sizeof(*pexclk), GFP_KERNEL);
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if (!pexclk)
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return -ENOMEM;
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pexclk->dev = &pdev->dev;
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for (i = 0; i < 2; ++i) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res) {
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dev_err(pexclk->dev, "Failed to get PEXCLK%d Address\n",
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i);
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return -ENOENT;
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}
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pexclk->regs[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pexclk->regs[i])) {
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ret = PTR_ERR(pexclk->regs[i]);
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dev_err(pexclk->dev, "Failed to IO map of PEXCLK%d: %d\n",
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i, ret);
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return ret;
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}
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}
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pexclk->prod_list = devm_tegra_prod_get(&pdev->dev);
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if (IS_ERR(pexclk->prod_list)) {
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dev_dbg(&pdev->dev, "Prod-settngs not available\n");
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pexclk->prod_list = NULL;
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} else {
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ret = tegra_prod_set_by_name(pexclk->regs, "prod",
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pexclk->prod_list);
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if (ret < 0) {
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dev_err(&pdev->dev, "Prod config failed: %d\n", ret);
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return ret;
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}
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}
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pexclk->pads = t194_pexclk_pads;
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pexclk->num_pads = ARRAY_SIZE(t194_pexclk_pads);
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pexclk->pinctrl_desc.name = "pinctrl-pexclk-padctrl";
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pexclk->pinctrl_desc.pctlops = &t194_pexclk_ops;
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pexclk->pinctrl_desc.confops = &t194_pexclk_pinconf_ops;
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pexclk->pinctrl_desc.pins = t194_pexclk_pins_desc;
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pexclk->pinctrl_desc.npins = ARRAY_SIZE(t194_pexclk_pins_desc);
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pexclk->pinctrl_desc.custom_params = t194_pexclk_cfg_params;
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pexclk->pinctrl_desc.num_custom_params =
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ARRAY_SIZE(t194_pexclk_cfg_params);
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pexclk->pctl = devm_pinctrl_register(pexclk->dev,
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&pexclk->pinctrl_desc,
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pexclk);
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if (IS_ERR(pexclk->pctl)) {
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ret = PTR_ERR(pexclk->pctl);
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dev_err(pexclk->dev, "Failed to register pinctrl: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, pexclk);
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return 0;
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}
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static const struct of_device_id t194_pexclk_of_match[] = {
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{
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.compatible = "nvidia,tegra194-pexclk-padctl",
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}, {
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},
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};
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MODULE_DEVICE_TABLE(of, t194_pexclk_of_match);
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static struct platform_driver tegra194_pexclk_pinctrl_driver = {
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.driver = {
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.name = "pinctrl-tegra194-pexclk-padctl",
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.of_match_table = t194_pexclk_of_match,
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},
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.probe = t194_pexclk_padctrl_probe,
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};
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static int __init tegra194_pexclk_padctrl_init(void)
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{
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return platform_driver_register(&tegra194_pexclk_pinctrl_driver);
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}
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postcore_initcall(tegra194_pexclk_padctrl_init);
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MODULE_DESCRIPTION("NVIDIA TEGRA194 PCIE PEXCLK Padcontrol Driver");
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MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
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MODULE_LICENSE("GPL v2");
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