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nvethernet: read pps output freq control

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Issue: Default 1 pulse (of width clk_ptp_ref_i) every
second.

Fix: The binary rollover is 2 Hz, and the digital
rollover is 1 Hz. low period of 537 ms and a high
period of 463 ms.

Bug 3462227

Change-Id: I5ec433af9e64e7709ba8e3d01261fe8a29d83198
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2641897
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rakesh Goyal
2021-12-14 16:34:31 +05:30
committed by Revanth Kumar Uppala
parent 41b780c228
commit 30a6d63eb2
1 changed files with 10 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/net/ethernet/nvidia/nvethernet/ether_linux.c
View File

@@ -5921,6 +5921,16 @@ static int ether_parse_dt(struct ether_priv_data *pdata)
if (ret_val < 0 || osi_core->m2m_role > OSI_PTP_M2M_SECONDARY) {
osi_core->m2m_role = OSI_PTP_M2M_INACTIVE;
}
/* Set PPS output control, 0 - default.
* 1 - Binary rollover is 2 Hz, and the digital rollover is 1 Hz.
*/
ret_val = of_property_read_u32(np, "nvidia,pps_op_ctrl",
&osi_core->pps_frq);
if (ret_val < 0 || osi_core->pps_frq > OSI_ENABLE) {
osi_core->pps_frq = OSI_DISABLE;
}
exit:
return ret;
}