nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-24 02:01:36 +03:00
Code Issues Packages Projects Releases Wiki Activity

drivers: pva: update SID programming for PVA

Browse Source 
Jira PVAAS-15366

Change-Id: Id0a541350afc62bb6d1eef59fb301b8650d16254
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3160296
Tested-by: Omar Nemri <onemri@nvidia.com>
Reviewed-by: Omar Nemri <onemri@nvidia.com>
Reviewed-by: Amruta Sai Anusha Bhamidipati <abhamidipati@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
omar
2024-05-13 17:03:33 +00:00
committed by Jon Hunter
parent ee9b187f9a
commit 35e17c237e
3 changed files with 23 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/video/tegra/host/pva/Makefile
View File

@@ -17,6 +17,7 @@ ccflags-y += -DTEGRA_OOT_MODULE
ccflags-y += -DCONFIG_TEGRA_T26X_GRHOST_PVA
ccflags-y += -DNVPVA_CONFIG_T264
ccflags-y += -DCONFIG_PVA_CO_DISABLED_T264
nvhost-pva-objs = \
pva.o \
@@ -53,4 +54,5 @@ nvhost-pva-objs = \
obj-m += nvhost-pva.o
endif
endif
endif

2
drivers/video/tegra/host/pva/pva_cntxt_dev_name_t264.h
View File

@@ -15,5 +15,5 @@
*/
#ifndef __PVA_CNTXT_DEV_NAME_T264_H__
#define __PVA_CNTXT_DEV_NAME_T264_H__
#define PVA_CNTXT_DEV_NAME_T264 "\"pva0_niso1_ctx8\","
#define PVA_CNTXT_DEV_NAME_T264 "pva0_niso1_ctx8"
#endif

39
drivers/video/tegra/host/pva/pva_t264.h
View File

@@ -20,7 +20,7 @@
#ifndef __PVA_T264_H__
#define __PVA_T264_H__
static char *aux_dev_name_t264 = "818c000000.pva0:pva0_niso1_ctx7";
static char *aux_dev_name_t264 = "818c000000.pva0:pva0_niso1_ctx8";
static u32 aux_dev_name_len_t264 = 31;
struct nvhost_device_data t264_pva0_info = {
@@ -40,19 +40,19 @@ struct nvhost_device_data t264_pva0_info = {
.firmware_name = "nvhost_pva030.fw",
.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
.vm_regs = {
{0x240000, false, 0},
{0x240004, false, 0},
{0x240008, false, 0},
{0x24000c, false, 0},
{0x240010, false, 0},
{0x240014, false, 0},
{0x240018, false, 0},
{0x24001c, false, 0},
{0x240020, false, 0},
{0x240020, false, 8},
{0x240020, false, 16},
{0x240024, false, 0},
{0x240024, false, 8}
{0x240000, false, 0xFFFF0000},
{0x240004, false, 0xFFFF0000},
{0x240008, false, 0xFFFF0000},
{0x24000c, false, 0xFFFF0000},
{0x240010, false, 0xFFFF0000},
{0x240014, false, 0xFFFF0000},
{0x240018, false, 0xFFFF0000},
{0x24001c, false, 0xFFFF0000},
{0x240020, false, 0x00FF0000},
{0x240020, false, 0x00FF0008},
{0x240020, false, 0x00FF0010},
{0x240024, false, 0x00FF0000},
{0x240024, false, 0x00FF0008}
},
.poweron_reset = true,
.serialize = true,
@@ -60,14 +60,13 @@ struct nvhost_device_data t264_pva0_info = {
.can_powergate = true,
};
#if (defined(CONFIG_PVA_CO_DISABLED) || defined(CONFIG_TEGRA_T26X_GRHOST_PVA))
static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 7,
8, 8, 8, 8, 8, 0, 0, 0};
#if defined(CONFIG_PVA_CO_DISABLED_T264)
static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 8,
9, 9, 9, 9, 9, 0, 0, 0};
#else
static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 7,
8, 0, 9, 0, 0, 0, 0, 0};
static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 8,
9, 0, 9, 0, 0, 0, 0, 0};
#endif
static u32 vm_regs_reg_idx_t264[] = {0, 1, 2, 3, 4, 5, 6, 7,
8, 8, 8, 9, 9, 0, 0, 0};
#endif