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ASoC: tegra-alt: remove unused macros for xbar
Some of the macros defined in tegra210_xbar_alt.h are not used anywhere, hence removed such macros. Also fixed lines to respect 80 character limit per line. Bug 200503387 Change-Id: Ieeb32ef62180fc6ae41e978ac54fb89d44a2486a Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2143068 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sameer Pujar
@@ -1,7 +1,7 @@
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/*
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* tegra210_xbar_alt.h - TEGRA210 XBAR registers
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -31,123 +31,48 @@
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/* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
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#define TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24
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#define TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f
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#define TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
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/* Channel count minus 1 */
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
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/* Channel count minus 1 */
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
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#define TEGRA210_AUDIOCIF_BITS_RVDS 0
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#define TEGRA210_AUDIOCIF_BITS_8 1
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#define TEGRA210_AUDIOCIF_BITS_12 2
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#define TEGRA210_AUDIOCIF_BITS_16 3
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#define TEGRA210_AUDIOCIF_BITS_20 4
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#define TEGRA210_AUDIOCIF_BITS_24 5
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#define TEGRA210_AUDIOCIF_BITS_28 6
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#define TEGRA210_AUDIOCIF_BITS_32 7
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA210_AUDIOCIF_BITS_8 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA210_AUDIOCIF_BITS_12 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA210_AUDIOCIF_BITS_16 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA210_AUDIOCIF_BITS_20 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA210_AUDIOCIF_BITS_24 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA210_AUDIOCIF_BITS_28 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA210_AUDIOCIF_BITS_32 << TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA210_AUDIOCIF_BITS_8 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA210_AUDIOCIF_BITS_12 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA210_AUDIOCIF_BITS_16 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA210_AUDIOCIF_BITS_20 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA210_AUDIOCIF_BITS_24 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA210_AUDIOCIF_BITS_28 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA210_AUDIOCIF_BITS_32 << TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
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#define TEGRA210_AUDIOCIF_EXPAND_ZERO 0
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#define TEGRA210_AUDIOCIF_EXPAND_ONE 1
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#define TEGRA210_AUDIOCIF_EXPAND_LFSR 2
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#define TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT 6
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#define TEGRA210_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA210_AUDIOCIF_EXPAND_ZERO << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA210_AUDIOCIF_EXPAND_ONE << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA210_AUDIOCIF_EXPAND_LFSR << TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT)
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#define TEGRA210_AUDIOCIF_STEREO_CONV_CH0 0
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#define TEGRA210_AUDIOCIF_STEREO_CONV_CH1 1
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#define TEGRA210_AUDIOCIF_STEREO_CONV_AVG 2
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#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4
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#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA210_AUDIOCIF_STEREO_CONV_CH0 << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA210_AUDIOCIF_STEREO_CONV_CH1 << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA210_AUDIOCIF_STEREO_CONV_AVG << TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_REPLICATE_SHIFT 3
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#define TEGRA210_AUDIOCIF_TRUNCATE_ROUND 0
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#define TEGRA210_AUDIOCIF_TRUNCATE_CHOP 1
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#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1
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#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA210_AUDIOCIF_TRUNCATE_ROUND << TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA210_AUDIOCIF_TRUNCATE_CHOP << TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
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#define TEGRA210_AUDIOCIF_MONO_CONV_ZERO 0
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#define TEGRA210_AUDIOCIF_MONO_CONV_COPY 1
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#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0
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#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA210_AUDIOCIF_MONO_CONV_ZERO << TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
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#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA210_AUDIOCIF_MONO_CONV_COPY << TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
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/* Fields in *AHUBRAMCTL_CTRL; used by different AHUB modules */
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#define TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_SHIFT 31
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#define TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY (1 << TEGRA210_AHUBRAMCTL_CTRL_READ_BUSY_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_READ_COUNT_SHIFT 16
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#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_READ_COUNT_MASK (0xff << TEGRA210_AHUBRAMCTL_CTRL_SEQ_READ_COUNT_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT 14
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_READ (0 << TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE (1 << TEGRA210_AHUBRAMCTL_CTRL_RW_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_SHIFT 13
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#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN (1 << TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_SHIFT 12
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#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_MASK (1 << TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT 0
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#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK (0x1ff << TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT)
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_READ 0
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE (1 << 14)
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#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN (1 << 13)
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#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN (1 << 12)
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#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK 0x1ff
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#define TEGRA210_NUM_DAIS 67
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#define TEGRA210_NUM_MUX_WIDGETS 50
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#define TEGRA210_NUM_MUX_INPUT 54 /* size of TEGRA210_ROUTES */
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#define TEGRA186_NUM_DAIS 108
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#define TEGRA186_NUM_MUX_WIDGETS 79
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#define TEGRA186_NUM_MUX_INPUT 82 /* size of TEGRA_ROUTES + TEGRA186_ROUTES */
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#define TEGRA210_NUM_MUX_WIDGETS 50
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#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX +\
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/* size of TEGRA210_ROUTES */
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#define TEGRA210_NUM_MUX_INPUT 54
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#define TEGRA186_NUM_DAIS 108
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#define TEGRA186_NUM_MUX_WIDGETS 79
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/* size of TEGRA_ROUTES + TEGRA186_ROUTES */
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#define TEGRA186_NUM_MUX_INPUT 82
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#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
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#define TEGRA186_XBAR_PART3_RX 0x600
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#define TEGRA186_XBAR_PART3_RX 0x600
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#define TEGRA186_XBAR_AUDIO_RX_COUNT 115
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#define TEGRA186_AUDIOCIF_CTRL_FIFO_SIZE_DOWNSHIFT_SHIFT 2
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#define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX +\
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(TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
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@@ -156,18 +81,18 @@
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#define TEGRA210_XBAR_REG_MASK_1 0x3f30031f
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#define TEGRA210_XBAR_REG_MASK_2 0xff1cf313
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#define TEGRA210_XBAR_REG_MASK_3 0x0
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#define TEGRA210_XBAR_UPDATE_MAX_REG 3
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#define TEGRA210_XBAR_UPDATE_MAX_REG 3
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#define TEGRA186_XBAR_REG_MASK_0 0xF3FFFFF
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#define TEGRA186_XBAR_REG_MASK_1 0x3F310F1F
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#define TEGRA186_XBAR_REG_MASK_2 0xFF3CF311
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#define TEGRA186_XBAR_REG_MASK_3 0x3F0F00FF
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#define TEGRA186_XBAR_UPDATE_MAX_REG 4
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#define TEGRA186_XBAR_UPDATE_MAX_REG 4
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#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
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/* T210 Modules Base address */
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#define T210_ADMAIF_BASE_ADDR 0x702d0000
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#define T210_ADMAIF_BASE_ADDR 0x702d0000
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#define T210_I2S1_BASE_ADDR 0x702d1000
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#define T210_I2S2_BASE_ADDR 0x702d1100
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#define T210_I2S3_BASE_ADDR 0x702d1200
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@@ -191,15 +116,15 @@
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#define T210_MVC2_BASE_ADDR 0x702da200
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#define T210_IQC1_BASE_ADDR 0x702de000
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#define T210_IQC2_BASE_ADDR 0x702de200
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#define T210_DMIC1_BASE_ADDR 0x702d4000
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#define T210_DMIC2_BASE_ADDR 0x702d4100
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#define T210_DMIC3_BASE_ADDR 0x702d4200
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#define T210_DMIC1_BASE_ADDR 0x702d4000
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#define T210_DMIC2_BASE_ADDR 0x702d4100
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#define T210_DMIC3_BASE_ADDR 0x702d4200
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#define T210_OPE1_BASE_ADDR 0x702d8000
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#define T210_OPE2_BASE_ADDR 0x702d8400
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#define T210_AMIXER1_BASE_ADDR 0x702dbb00
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#define T210_AMIXER1_BASE_ADDR 0x702dbb00
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/* T186 Modules Base address */
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#define T186_ADMAIF_BASE_ADDR 0x0290F000
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#define T186_ADMAIF_BASE_ADDR 0x0290F000
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#define T186_I2S1_BASE_ADDR 0x02901000
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#define T186_I2S2_BASE_ADDR 0x02901100
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#define T186_I2S3_BASE_ADDR 0x02901200
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@@ -228,16 +153,16 @@
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#define T186_MVC2_BASE_ADDR 0x0290A200
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#define T186_IQC1_BASE_ADDR 0x0290E000
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#define T186_IQC2_BASE_ADDR 0x0290E200
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#define T186_DMIC1_BASE_ADDR 0x02904000
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#define T186_DMIC2_BASE_ADDR 0x02904100
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#define T186_DMIC3_BASE_ADDR 0x02904200
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#define T186_DMIC4_BASE_ADDR 0x02904300
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#define T186_DMIC1_BASE_ADDR 0x02904000
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#define T186_DMIC2_BASE_ADDR 0x02904100
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#define T186_DMIC3_BASE_ADDR 0x02904200
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#define T186_DMIC4_BASE_ADDR 0x02904300
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#define T186_OPE1_BASE_ADDR 0x02908000
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#define T186_AMIXER1_BASE_ADDR 0x0290BB00
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#define T186_ASRC1_BASE_ADDR 0x02910000
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#define T186_ARAD1_BASE_ADDR 0x0290E400
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#define T186_DSPK1_BASE_ADDR 0x02905000
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#define T186_DSPK2_BASE_ADDR 0x02905100
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#define T186_AMIXER1_BASE_ADDR 0x0290BB00
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#define T186_ASRC1_BASE_ADDR 0x02910000
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#define T186_ARAD1_BASE_ADDR 0x0290E400
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#define T186_DSPK1_BASE_ADDR 0x02905000
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#define T186_DSPK2_BASE_ADDR 0x02905100
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struct tegra210_xbar_cif_conf {
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@@ -87,8 +87,7 @@ void tegra210_xbar_write_ahubram(struct regmap *regmap, unsigned int reg_ctrl,
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unsigned int val = 0;
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int i = 0;
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val = (ram_offset << TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT) &
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TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK;
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val = ram_offset & TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK;
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val |= TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN;
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val |= TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN;
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val |= TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE;
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@@ -108,8 +107,7 @@ void tegra210_xbar_read_ahubram(struct regmap *regmap, unsigned int reg_ctrl,
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unsigned int val = 0;
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int i = 0;
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val = (ram_offset << TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_SHIFT) &
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TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK;
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val = ram_offset & TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK;
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val |= TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN;
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val |= TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN;
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val |= TEGRA210_AHUBRAMCTL_CTRL_RW_READ;
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