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ASoC: tegra: remove 'tegra-alt' directory

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As part of upstream alignment all audio drivers have been moved to
'tegra' path and are upgraded to work with 5.9 kernel. References
to older versions can be removed now. Earlier these were moved to
retain the commit history.

Summary on files that are being removed:
 * Legacy FPGA code is dropped
 * PCM driver changes already integrated
 * ASoC Utils changes already integrated
 * Makefile/Kconfig changes are aligned as per upstream plan

Bug 2845498

Change-Id: I645f94852d7137915ff4045be31e5a943a3fa6b3
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2364087
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sameer Pujar
2020-06-19 18:47:35 +05:30
parent 07de08349a
commit 41ff9ddcfe
8 changed files with 0 additions and 2899 deletions
Download Patch File Download Diff File Expand all files Collapse all files

230
sound/soc/tegra-alt/Kconfig
View File

@@ -1,230 +0,0 @@
if SND_SOC
config SND_SOC_TEGRA_ALT_186
def_bool y
depends on SND_SOC_TEGRA_ALT
depends on ARCH_TEGRA_18x_SOC
config SND_SOC_TEGRA186_DSPK_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_186
config SND_SOC_TEGRA186_ASRC_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_186
config SND_SOC_TEGRA186_ARAD_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_186
config SND_SOC_TEGRA_T186REF_P4573_ALT
tristate "SoC Audio support for P4573 with CS53L30 and RT5658"
depends on SND_SOC_TEGRA_T186REF_ALT
select SND_SOC_CS53L30
select SND_SOC_RT5659
help
Say Y or M here.
config SND_SOC_TEGRA_T186REF_AUTO_ALT
tristate "SoC Audio support for T186Ref Automotive"
depends on SND_SOC_TEGRA_T186REF_ALT
help
Say Y or M here.
config SND_SOC_TEGRA186_ARAD_WAR
def_bool y
depends on SND_SOC_TEGRA186_ARAD_ALT
depends on TEGRA186_AHC
config SND_SOC_TEGRA186_ASRC_WAR
def_bool n
depends on SND_SOC_TEGRA186_ASRC_ALT
depends on SND_SOC_TEGRA186_ARAD_WAR
config SND_SOC_TEGRA_ALT
tristate "Alternative DAPM-based SoC audio support for the Tegra System-on-Chip"
depends on ARCH_TEGRA
depends on SND_DMAENGINE_PCM
select REGMAP_MMIO
select SND_DYNAMIC_MINORS
help
Say Y or M here if you want support for SoC audio on Tegra, using the
alternative driver that exposes to user-space the full routing capabilities
of the AHUB (Audio HUB) hardware module.
config SND_SOC_TEGRA_ALT_210
def_bool y
depends on SND_SOC_TEGRA_ALT
config SND_SOC_TEGRA210_XBAR_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_ADMAIF_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_I2S_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_DMIC_ALT
tristate
def_tristate SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_AMX_ALT
tristate
def_tristate SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_ADX_ALT
tristate
def_tristate SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_MIXER_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_SFC_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_AFC_ALT
tristate
def_tristate SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_MVC_ALT
tristate
def_tristate SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_IQC_ALT
tristate "Tegra210 IQC driver"
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
help
Say Y or M if you want to add support for Tegra210 IQC module.
config SND_SOC_TEGRA210_OPE_ALT
tristate
def_tristate SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210
config SND_SOC_TEGRA210_ADSP_ALT
tristate
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210 && TEGRA_NVADSP
select SND_SOC_COMPRESS
config DISABLE_ADSP_AUDIO
bool "Disable ADSP Audio Driver"
def_bool n
depends on SND_SOC_TEGRA_ALT && SND_SOC_TEGRA_ALT_210 && TEGRA_NVADSP
help
Say Y if you want to disable support for Tegra210 ADSP module
config SND_SOC_TEGRA_T210REF_ALT
tristate "SoC Audio support for T210Ref"
depends on SND_SOC_TEGRA_ALT
depends on ARCH_TEGRA_210_SOC
select SND_SOC_TEGRA210_XBAR_ALT
select SND_SOC_TEGRA210_PCM_ALT
select SND_SOC_TEGRA210_ADMA_ALT
select SND_SOC_TEGRA210_ADMAIF_ALT
select SND_SOC_TEGRA210_I2S_ALT
select SND_SOC_TEGRA210_DMIC_ALT
select SND_SOC_TEGRA210_AMX_ALT
select SND_SOC_TEGRA210_ADX_ALT
select SND_SOC_TEGRA210_MIXER_ALT
select SND_SOC_TEGRA210_SFC_ALT
select SND_SOC_TEGRA210_AFC_ALT
select SND_SOC_TEGRA210_MVC_ALT
select SND_SOC_TEGRA210_OPE_ALT
select SND_SOC_TEGRA210_ADSP_ALT if TEGRA_NVADSP && !DISABLE_ADSP_AUDIO
select SND_SOC_TEGRA_ASOC_HWDEP_ALT
select SND_SOC_SPDIF
select SND_SOC_AD193X_I2C
help
Say Y or M here.
config SND_SOC_TEGRA_T186REF_ALT
tristate "SoC Audio support for T186Ref"
depends on SND_SOC_TEGRA_ALT
depends on ARCH_TEGRA_18x_SOC
select SND_SOC_TEGRA210_XBAR_ALT
select SND_SOC_TEGRA210_PCM_ALT
select SND_SOC_TEGRA210_ADMA_ALT
select SND_SOC_TEGRA210_ADMAIF_ALT
select SND_SOC_TEGRA210_I2S_ALT
select SND_SOC_TEGRA210_DMIC_ALT
select SND_SOC_TEGRA210_AMX_ALT
select SND_SOC_TEGRA210_ADX_ALT
select SND_SOC_TEGRA210_MIXER_ALT
select SND_SOC_TEGRA210_SFC_ALT
select SND_SOC_TEGRA210_AFC_ALT
select SND_SOC_TEGRA210_MVC_ALT
select SND_SOC_TEGRA210_OPE_ALT
select SND_SOC_TEGRA210_ADSP_ALT if TEGRA_NVADSP && !DISABLE_ADSP_AUDIO
select SND_SOC_TEGRA186_ASRC_ALT
select SND_SOC_TEGRA186_ARAD_ALT
select SND_SOC_TEGRA186_DSPK_ALT
select SND_SOC_TEGRA_ASOC_HWDEP_ALT
select SND_SOC_SPDIF
select SND_SOC_COMPRESS
help
Say Y or M here.
config SND_SOC_TEGRA210_AUDIO_ALT
tristate "SoC Audio support for Tegra210"
depends on I2C
depends on ARCH_TEGRA_210_SOC || ARCH_TEGRA_18x_SOC
select SND_SOC_TEGRA210_XBAR_ALT
select SND_SOC_TEGRA210_PCM_ALT
select SND_SOC_TEGRA210_ADMA_ALT
select SND_SOC_TEGRA210_ADMAIF_ALT
select SND_SOC_TEGRA210_I2S_ALT
select SND_SOC_TEGRA210_DMIC_ALT
select SND_SOC_TEGRA210_AMX_ALT
select SND_SOC_TEGRA210_ADX_ALT
select SND_SOC_TEGRA210_MIXER_ALT
select SND_SOC_TEGRA210_SFC_ALT
select SND_SOC_TEGRA210_AFC_ALT
select SND_SOC_TEGRA210_MVC_ALT
select SND_SOC_TEGRA210_OPE_ALT
select SND_SOC_TEGRA210_ADSP_ALT if TEGRA_NVADSP && !DISABLE_ADSP_AUDIO
select SND_SOC_TEGRA186_ASRC_ALT if ARCH_TEGRA_18x_SOC
select SND_SOC_TEGRA186_ARAD_ALT if ARCH_TEGRA_18x_SOC
select SND_SOC_TEGRA186_DSPK_ALT if ARCH_TEGRA_18x_SOC
select SND_SOC_SPDIF
select SND_SOC_COMPRESS
select SND_SOC_RT5640
select SND_SOC_RT5659
select SND_SOC_SGTL5000
help
Say Y or M here if you want to enable support for ASoC machine driver on
Tegra210 and successor platforms like Tegra186, Tegra194.
config SND_SOC_TEGRA_T210REF_P2382_ALT
tristate "SoC Audio support for P2382Ref T210"
depends on SND_SOC_TEGRA_ALT
depends on ARCH_TEGRA_210_SOC
select SND_SOC_TEGRA210_XBAR_ALT
select SND_SOC_TEGRA210_PCM_ALT
select SND_SOC_TEGRA210_ADMA_ALT
select SND_SOC_TEGRA210_ADMAIF_ALT
select SND_SOC_TEGRA210_I2S_ALT
select SND_SOC_TEGRA210_AMX_ALT
select SND_SOC_TEGRA210_ADX_ALT
select SND_SOC_TEGRA210_MIXER_ALT
select SND_SOC_TEGRA210_SFC_ALT
select SND_SOC_TEGRA210_AFC_ALT
select SND_SOC_TEGRA210_MVC_ALT
select SND_SOC_TEGRA210_OPE_ALT
select SND_SOC_TEGRA210_ADSP_ALT if TEGRA_NVADSP && !DISABLE_ADSP_AUDIO
select SND_SOC_TEGRA_ASOC_HWDEP_ALT
select SND_SOC_SPDIF
help
Say Y or M here
endif

77
sound/soc/tegra-alt/Makefile
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@@ -1,77 +0,0 @@
GCOV_PROFILE := y
subdir-ccflags-y := -Werror
subdir-ccflags-y += -I$(srctree)
subdir-ccflags-y += -I$(srctree)/sound/soc/codecs/
subdir-ccflags-y += -I$(srctree.nvidia)
subdir-ccflags-y += -I$(srctree.nvidia)/sound/soc/tegra-virt-alt/
subdir-ccflags-y += -I$(srctree.nvidia)/sound/soc/tegra-alt/include/
#----------------------------- utility drivers --------------------------------------
CFLAGS_tegra_pcm_alt.o += -Wno-shift-count-overflow
snd-soc-tegra-alt-utils-objs := utils/tegra_asoc_utils_alt.o \
utils/tegra_pcm_alt.o \
utils/tegra_asoc_machine_alt.o \
utils/tegra_asoc_dt_parser.o \
utils/tegra_isomgr_bw_alt.o \
utils/ahub_unit_fpga_clock.o \
utils/tegra210_xbar_utils_alt.o
obj-$(CONFIG_SND_SOC_TEGRA_ALT) += snd-soc-tegra-alt-utils.o
#----------------------------- platform drivers -------------------------------------
snd-soc-tegra210-alt-admaif-objs := tegra210_admaif_alt.o
snd-soc-tegra210-alt-xbar-objs := tegra210_xbar_alt.o
snd-soc-tegra210-alt-i2s-objs := tegra210_i2s_alt.o
snd-soc-tegra210-alt-dmic-objs := tegra210_dmic_alt.o
snd-soc-tegra210-alt-amx-objs := tegra210_amx_alt.o
snd-soc-tegra210-alt-adx-objs := tegra210_adx_alt.o
snd-soc-tegra210-alt-mixer-objs := tegra210_mixer_alt.o
snd-soc-tegra210-alt-sfc-objs := tegra210_sfc_alt.o
snd-soc-tegra210-alt-afc-objs := tegra210_afc_alt.o
snd-soc-tegra210-alt-mvc-objs := tegra210_mvc_alt.o
snd-soc-tegra210-alt-iqc-objs := tegra210_iqc_alt.o
snd-soc-tegra210-alt-adsp-objs := tegra210_adsp_alt.o
snd-soc-tegra186-alt-asrc-objs := tegra186_asrc_alt.o
snd-soc-tegra186-alt-arad-objs := tegra186_arad_alt.o
snd-soc-tegra186-alt-dspk-objs := tegra186_dspk_alt.o
snd-soc-tegra210-alt-ope-objs := tegra210_ope_alt.o \
tegra210_peq_alt.o \
tegra210_mbdrc_alt.o
obj-$(CONFIG_SND_SOC_TEGRA210_ADMAIF_ALT) += snd-soc-tegra210-alt-admaif.o
obj-$(CONFIG_SND_SOC_TEGRA210_XBAR_ALT) += snd-soc-tegra210-alt-xbar.o
obj-$(CONFIG_SND_SOC_TEGRA210_I2S_ALT) += snd-soc-tegra210-alt-i2s.o
obj-$(CONFIG_SND_SOC_TEGRA210_DMIC_ALT) += snd-soc-tegra210-alt-dmic.o
obj-$(CONFIG_SND_SOC_TEGRA210_AMX_ALT) += snd-soc-tegra210-alt-amx.o
obj-$(CONFIG_SND_SOC_TEGRA210_ADX_ALT) += snd-soc-tegra210-alt-adx.o
obj-$(CONFIG_SND_SOC_TEGRA210_MIXER_ALT) += snd-soc-tegra210-alt-mixer.o
obj-$(CONFIG_SND_SOC_TEGRA210_SFC_ALT) += snd-soc-tegra210-alt-sfc.o
obj-$(CONFIG_SND_SOC_TEGRA210_AFC_ALT) += snd-soc-tegra210-alt-afc.o
obj-$(CONFIG_SND_SOC_TEGRA210_MVC_ALT) += snd-soc-tegra210-alt-mvc.o
obj-$(CONFIG_SND_SOC_TEGRA210_IQC_ALT) += snd-soc-tegra210-alt-iqc.o
obj-$(CONFIG_SND_SOC_TEGRA210_OPE_ALT) += snd-soc-tegra210-alt-ope.o
obj-$(CONFIG_SND_SOC_TEGRA210_ADSP_ALT) += snd-soc-tegra210-alt-adsp.o
obj-$(CONFIG_SND_SOC_TEGRA186_ARAD_ALT) += snd-soc-tegra186-alt-arad.o
obj-$(CONFIG_SND_SOC_TEGRA186_ASRC_ALT) += snd-soc-tegra186-alt-asrc.o
obj-$(CONFIG_SND_SOC_TEGRA186_DSPK_ALT) += snd-soc-tegra186-alt-dspk.o
#------------------------------------ machine drivers ---------------------------------------
snd-soc-tegra-alt-p1889ref-objs := machine_drivers/tegra_p1889ref_alt.o
snd-soc-tegra-alt-t210ref-objs := machine_drivers/tegra_t210ref_alt.o
snd-soc-tegra-alt-t186ref-objs := machine_drivers/tegra_t186ref_alt.o
snd-soc-tegra-machine-driver-mobile-objs := machine_drivers/tegra_machine_driver_mobile.o
snd-soc-tegra-alt-t186ref-p2382-objs := machine_drivers/tegra_t186ref_p2382_alt.o
snd-soc-tegra-alt-t186ref-p4573-objs := machine_drivers/tegra_t186ref_p4573_alt.o
snd-soc-tegra-alt-t210ref-p2382-objs := machine_drivers/tegra_t210ref_p2382_alt.o \
machine_drivers/tegra_maui_alt.o
obj-$(CONFIG_SND_SOC_TEGRA_P1889REF_ALT) += snd-soc-tegra-alt-p1889ref.o
obj-$(CONFIG_SND_SOC_TEGRA_T210REF_ALT) += snd-soc-tegra-alt-t210ref.o
obj-$(CONFIG_SND_SOC_TEGRA_T210REF_P2382_ALT) += snd-soc-tegra-alt-t210ref-p2382.o
obj-$(CONFIG_SND_SOC_TEGRA_T186REF_FPGA_ALT) += snd-soc-tegra-alt-t186ref.o
obj-$(CONFIG_SND_SOC_TEGRA210_AUDIO_ALT) += snd-soc-tegra-machine-driver-mobile.o
obj-$(CONFIG_SND_SOC_TEGRA_T186REF_AUTO_ALT) += snd-soc-tegra-alt-t186ref-p2382.o
obj-$(CONFIG_SND_SOC_TEGRA_T186REF_P4573_ALT) += snd-soc-tegra-alt-t186ref-p4573.o

481
sound/soc/tegra-alt/include/ahub_unit_fpga_clock.h
View File

@@ -1,481 +0,0 @@
/*
* ahub_unit_fpga_clock.h
*
* Copyright (c) 2013-2017, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef __AHUB_UNIT_FPGA_CLOCK_H__
#define __AHUB_UNIT_FPGA_CLOCK_H__
#define SYSTEM_FPGA 0
#define DEBUG_FPGA 1
#define APE_FPGA_MISC_CLK_SOURCE_I2C1_0 0x68
#define APE_FPGA_MISC_CLK_SOURCE_I2S1_0 0x28
#define APE_FPGA_MISC_CLK_SOURCE_I2S2_0 0x20
#define APE_FPGA_MISC_CLK_SOURCE_I2S3_0 0x24
#define APE_FPGA_MISC_CLK_SOURCE_I2S4_0 0x2c
#define APE_FPGA_MISC_CLK_SOURCE_I2S5_0 0x30
#define APE_FPGA_MISC_CLK_SOURCE_DMIC1_0 0x14
#define I2C_I2C_CMD_ADDR0_0 0x4
#define I2C_I2C_CNFG_0 0x0
#define I2C_I2C_CMD_DATA1_0 0xc
#define I2C_I2C_CONFIG_LOAD_0 0x8c
#define I2C_I2C_STATUS_0 0x1c
#define I2C_I2C_CMD_ADDR1_0 0x8
#define I2C_I2C_CMD_DATA1_0 0xc
#define I2C_I2C_CMD_DATA2_0 0x10
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0 0x1d8
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0 0x100
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0 0x104
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0 0x3bc
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0 0x3c0
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0 0x4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0 0x10
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0 0x124
#define PINMUX_AUX_GEN1_I2C_SDA_0 0x30c0
#define PINMUX_AUX_GEN1_I2C_SCL_0 0x30bc
#define PINMUX_AUX_DAP1_SCLK_0 0x3130
#define PINMUX_AUX_DAP1_FS_0 0x3124
#define PINMUX_AUX_DAP1_DIN_0 0x3128
#define PINMUX_AUX_DAP1_DOUT_0 0x312c
#define PINMUX_AUX_DAP2_SCLK_0 0x3140
#define PINMUX_AUX_DAP2_FS_0 0x3134
#define PINMUX_AUX_DAP2_DIN_0 0x3138
#define PINMUX_AUX_DAP2_DOUT_0 0x313c
#define PINMUX_AUX_DMIC1_CLK_0 0x30a4 /* DAP3_SCLK_0 */
#define PINMUX_AUX_DMIC1_DAT_0 0x30a8 /* DAP3_FS_0 */
#define PINMUX_AUX_DMIC2_CLK_0 0x30ac /* DAP3_DIN_0 */
#define PINMUX_AUX_DMIC2_DAT_0 0x30b0 /* DAP3_DOUT_0 */
#define PINMUX_AUX_GPIO_PK0_0 0x3254 /* DAP5 */
#define PINMUX_AUX_GPIO_PK1_0 0x3258 /* DAP5 */
#define PINMUX_AUX_GPIO_PK2_0 0x325c /* DAP5 */
#define PINMUX_AUX_GPIO_PK3_0 0x3260 /* DAP5 */
#define NV_ADDRESS_MAP_APE_AHUB_FPGA_CAR_BASE 1882050560
#define NV_ADDRESS_MAP_APE_AHUB_FPGA_CAR_LIMIT 1882054655
#define NV_ADDRESS_MAP_APE_AHUB_FPGA_CAR_SIZE 4096
#define T210_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_BASE 1882048512
#define T186_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_BASE 0x0290C800
#define T210_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_LIMIT 1882048767
#define T186_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_LIMIT 0x0290C8FF
#define NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_SIZE 256
#if SYSTEM_FPGA
#define T210_NV_ADDRESS_MAP_APE_AHUB_I2C_BASE 0x7000c000
#else
#define T210_NV_ADDRESS_MAP_APE_AHUB_I2C_BASE 1882047744
#define T186_NV_ADDRESS_MAP_APE_AHUB_I2C_BASE 0x0290c500
#define NV_ADDRESS_MAP_APE_AHUB_GPIO_BASE 0x702DC700
#define APE_AHUB_GPIO_CNF_0 0x0
#define APE_AHUB_GPIO_OE_0 0x10
#define APE_AHUB_GPIO_OUT_0 0x20
#endif
#define NV_ADDRESS_MAP_APE_AHUB_I2C_LIMIT 1882048255
#define NV_ADDRESS_MAP_APE_AHUB_I2C_SIZE 512
#define NV_ADDRESS_MAP_APB_PP_BASE 1879048192
#define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE 1610637312
#define T210_NV_ADDRESS_MAP_APE_I2S5_BASE 0x702d1400
#define T186_NV_ADDRESS_MAP_APE_I2S5_BASE 0x02901400
#define I2S5_CYA_0 0xb0
#define APE_FPGA_MISC_CLK_SOURCE_DSPK1_0 0x6c
#define APE_FPGA_MISC_CLK_SOURCE_DSPK2_0 0x70
#define CDCE906_04_0960_MHz 0
#define CDCE906_06_1440_MHz 1
#define CDCE906_08_1920_MHz 2
#define CDCE906_11_2896_MHz 3
#define CDCE906_12_2880_MHz 4
#define CDCE906_16_3840_MHz 5
#define CDCE906_22_5792_MHz 6
#define CDCE906_24_5760_MHz 7
#define CDCE906_09_2160_MHz 8
#define CDCE906_16_9344_MHz 9
#define CDCE906_18_4320_MHz 10
#define CDCE906_33_8688_MHz 11
#define CDCE906_36_8640_MHz 12
#define MAX9485_DEVICE_ADDRESS 0x60
#define MAX9485_MCLK_FREQ_163840 0x31
#define MAX9485_MCLK_FREQ_112896 0x22
#define MAX9485_MCLK_FREQ_122880 0x23
#define MAX9485_MCLK_FREQ_225792 0x32
#define MAX9485_MCLK_FREQ_245760 0x33
enum AUDIO_DAC_DATAWIDTH{
AUDIO_DAC_DATAWIDTH_16 = 3,
AUDIO_DAC_DATAWIDTH_24 = 5
};
enum AUDIO_SAMPLE_RATE{
AUDIO_SAMPLE_RATE_8_00 = 8000,
AUDIO_SAMPLE_RATE_11_02 = 11020,
AUDIO_SAMPLE_RATE_12_00 = 12000,
AUDIO_SAMPLE_RATE_16_00 = 16000,
AUDIO_SAMPLE_RATE_22_05 = 22050,
AUDIO_SAMPLE_RATE_24_00 = 24000,
AUDIO_SAMPLE_RATE_32_00 = 32000,
AUDIO_SAMPLE_RATE_44_10 = 44100,
AUDIO_SAMPLE_RATE_48_00 = 48000,
AUDIO_SAMPLE_RATE_64_00 = 64000,
AUDIO_SAMPLE_RATE_88_20 = 88200,
AUDIO_SAMPLE_RATE_96_00 = 96000,
AUDIO_SAMPLE_RATE_128_00 = 128000,
AUDIO_SAMPLE_RATE_176_40 = 176000,
AUDIO_SAMPLE_RATE_192_00 = 192000
};
enum I2S_ID{
I2S1 = 0,
I2S2,
I2S3,
I2S4,
I2S5
};
enum AUDIO_MASTER_CLK_FREQ{
CLK_OUT_3_0720_MHZ = 0,
CLK_OUT_4_0960_MHZ,
CLK_OUT_4_6080_MHZ,
CLK_OUT_5_6448_MHZ,
CLK_OUT_6_1440_MHZ,
CLK_OUT_8_1920_MHZ,
CLK_OUT_11_2896_MHZ,
CLK_OUT_12_2888_MHZ,
CLK_OUT_16_3840_MHZ,
CLK_OUT_16_9344_MHZ,
CLK_OUT_18_4320_MHZ,
CLK_OUT_22_5792_MHZ,
CLK_OUT_24_5760_MHZ,
CLK_OUT_33_8688_MHZ,
CLK_OUT_36_8640_MHZ,
CLK_OUT_49_1520_MHZ,
CLK_OUT_73_7280_MHZ,
CLK_OUT_162_MHZ,
TOTAL_CLK_OUT
};
enum AUDIO_CLOCK_GEN_SELECT{
CLK_OUT_FROM_TEGRA,
CLK_GEN_CDCE906,
CLK_GEN_MAX9485
};
#define AD1937_X_ADDRESS 0x05
#define AD1937_Y_ADDRESS 0x04
#define AD1937_Z_ADDRESS 0x07
#define AD1937_PLL_CLK_CTRL_0 0x00
#define AD1937_PLL_CLK_CTRL_1 0x01
#define AD1937_DAC_CTRL_0 0x02
#define AD1937_DAC_CTRL_1 0x03
#define AD1937_DAC_CTRL_2 0x04
#define AD1937_DAC_MUTE_CTRL 0x05
#define AD1937_DAC_VOL_CTRL_DAC1L 0x06
#define AD1937_DAC_VOL_CTRL_DAC1R 0x07
#define AD1937_DAC_VOL_CTRL_DAC2L 0x08
#define AD1937_DAC_VOL_CTRL_DAC2R 0x09
#define AD1937_DAC_VOL_CTRL_DAC3L 0x0a
#define AD1937_DAC_VOL_CTRL_DAC3R 0x0b
#define AD1937_DAC_VOL_CTRL_DAC4L 0x0c
#define AD1937_DAC_VOL_CTRL_DAC4R 0x0d
#define AD1937_ADC_CTRL_0 0x0e
#define AD1937_ADC_CTRL_1 0x0f
#define AD1937_ADC_CTRL_2 0x10
#define AD1937_PLL_CLK_CTRL_0_PWR_MASK (1 << 0)
#define AD1937_PLL_CLK_CTRL_0_PWR_ON (0 << 0)
#define AD1937_PLL_CLK_CTRL_0_PWR_OFF (1 << 0)
#define AD1937_PLL_CLK_CTRL_0_MCLKI_MASK (3 << 1)
#define AD1937_PLL_CLK_CTRL_0_MCLKI_256 (0 << 1)
#define AD1937_PLL_CLK_CTRL_0_MCLKI_384 (1 << 1)
#define AD1937_PLL_CLK_CTRL_0_MCLKI_512 (2 << 1)
#define AD1937_PLL_CLK_CTRL_0_MCLKI_768 (3 << 1)
#define AD1937_PLL_CLK_CTRL_0_MCLKO_MASK (3 << 3)
#define AD1937_PLL_CLK_CTRL_0_MCLKO_XTAL (0 << 3)
#define AD1937_PLL_CLK_CTRL_0_MCLKO_256 (1 << 3)
#define AD1937_PLL_CLK_CTRL_0_MCLKO_512 (2 << 3)
#define AD1937_PLL_CLK_CTRL_0_MCLKO_OFF (3 << 3)
#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_MASK (3 << 5)
#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_MCLKI (0 << 5)
#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_DLRCLK (1 << 5)
#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_ALRCLK (2 << 5)
#define AD1937_PLL_CLK_CTRL_0_INTERNAL_MASTER_CLK_MASK (1 << 7)
#define AD1937_PLL_CLK_CTRL_0_INTERNAL_MASTER_CLK_DISABLE (0 << 7)
#define AD1937_PLL_CLK_CTRL_0_INTERNAL_MASTER_CLK_ENABLE (1 << 7)
#define AD1937_PLL_CLK_CTRL_1_DAC_CLK_MASK (1 << 0)
#define AD1937_PLL_CLK_CTRL_1_DAC_CLK_PLL (0 << 0)
#define AD1937_PLL_CLK_CTRL_1_DAC_CLK_MCLK (1 << 0)
#define AD1937_PLL_CLK_CTRL_1_ADC_CLK_MASK (1 << 1)
#define AD1937_PLL_CLK_CTRL_1_ADC_CLK_PLL (0 << 1)
#define AD1937_PLL_CLK_CTRL_1_ADC_CLK_MCLK (1 << 1)
#define AD1937_PLL_CLK_CTRL_1_VREF_MASK (1 << 2)
#define AD1937_PLL_CLK_CTRL_1_VREF_ENABLE (0 << 2)
#define AD1937_PLL_CLK_CTRL_1_VREF_DISABLE (1 << 2)
#define AD1937_PLL_CLK_CTRL_1_PLL_MASK (1 << 3)
#define AD1937_PLL_CLK_CTRL_1_PLL_NOT_LOCKED (0 << 3)
#define AD1937_PLL_CLK_CTRL_1_PLL_LOCKED (1 << 3)
#define AD1937_DAC_CTRL_0_PWR_MASK (1 << 0)
#define AD1937_DAC_CTRL_0_PWR_ON (0 << 0)
#define AD1937_DAC_CTRL_0_PWR_OFF (1 << 0)
#define AD1937_DAC_CTRL_0_SAMPLE_RATE_MASK (3 << 1)
#define AD1937_DAC_CTRL_0_SAMPLE_RATE_32_44_1_48_KHZ (0 << 1)
#define AD1937_DAC_CTRL_0_SAMPLE_RATE_64_88_2_96_KHZ (1 << 1)
#define AD1937_DAC_CTRL_0_SAMPLE_RATE_128_176_4_192_KHZ (2 << 1)
#define AD1937_DAC_CTRL_0_DSDATA_DELAY_MASK (7 << 3)
#define AD1937_DAC_CTRL_0_DSDATA_DELAY_1 (0 << 3)
#define AD1937_DAC_CTRL_0_DSDATA_DELAY_0 (1 << 3)
#define AD1937_DAC_CTRL_0_DSDATA_DELAY_8 (2 << 3)
#define AD1937_DAC_CTRL_0_DSDATA_DELAY_12 (3 << 3)
#define AD1937_DAC_CTRL_0_DSDATA_DELAY_16 (4 << 3)
#define AD1937_DAC_CTRL_0_FMT_MASK (3 << 6)
#define AD1937_DAC_CTRL_0_FMT_STEREO (0 << 6)
#define AD1937_DAC_CTRL_0_FMT_TDM_SINGLE_LINE (1 << 6)
#define AD1937_DAC_CTRL_0_FMT_TDM_AUX (2 << 6)
#define AD1937_DAC_CTRL_0_FMT_TDM_DUAL_LINE (3 << 6)
#define AD1937_DAC_CTRL_1_DBCLK_ACTIVE_EDGE_MASK (1 << 0)
#define AD1937_DAC_CTRL_1_DBCLK_ACTIVE_EDGE_MIDCYCLE (0 << 0)
#define AD1937_DAC_CTRL_1_DBCLK_ACTIVE_EDGE_PIPELINE (1 << 0)
#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_MASK (3 << 1)
#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_64 (0 << 1)
#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_128 (1 << 1)
#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_256 (2 << 1)
#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_512 (3 << 1)
#define AD1937_DAC_CTRL_1_DLRCLK_POLARITY_MASK (1 << 3)
#define AD1937_DAC_CTRL_1_DLRCLK_POLARITY_LEFT_LOW (0 << 3)
#define AD1937_DAC_CTRL_1_DLRCLK_POLARITY_LEFT_HIGH (1 << 3)
#define AD1937_DAC_CTRL_1_DLRCLK_MASK (1 << 4)
#define AD1937_DAC_CTRL_1_DLRCLK_SLAVE (0 << 4)
#define AD1937_DAC_CTRL_1_DLRCLK_MASTER (1 << 4)
#define AD1937_DAC_CTRL_1_DBCLK_MASK (1 << 5)
#define AD1937_DAC_CTRL_1_DBCLK_SLAVE (0 << 5)
#define AD1937_DAC_CTRL_1_DBCLK_MASTER (1 << 5)
#define AD1937_DAC_CTRL_1_DBCLK_SOURCE_MASK (1 << 6)
#define AD1937_DAC_CTRL_1_DBCLK_SOURCE_DBCLK_PIN (0 << 6)
#define AD1937_DAC_CTRL_1_DBCLK_SOURCE_INTERNAL (1 << 6)
#define AD1937_DAC_CTRL_1_DBCLK_POLARITY_MASK (1 << 7)
#define AD1937_DAC_CTRL_1_DBCLK_POLARITY_NORMAL (0 << 7)
#define AD1937_DAC_CTRL_1_DBCLK_POLARITY_INVERTED (1 << 7)
#define AD1937_DAC_CTRL_2_MASTER_MASK (1 << 0)
#define AD1937_DAC_CTRL_2_MASTER_UNMUTE (0 << 0)
#define AD1937_DAC_CTRL_2_MASTER_MUTE (1 << 0)
#define AD1937_DAC_CTRL_2_DEEMPHASIS_MASK (3 << 1)
#define AD1937_DAC_CTRL_2_DEEMPHASIS_FLAT (0 << 1)
#define AD1937_DAC_CTRL_2_DEEMPHASIS_48_KHZ (1 << 1)
#define AD1937_DAC_CTRL_2_DEEMPHASIS_44_1_KHZ (2 << 1)
#define AD1937_DAC_CTRL_2_DEEMPHASIS_32_KHZ (3 << 1)
#define AD1937_DAC_CTRL_2_WORD_WIDTH_MASK (3 << 3)
#define AD1937_DAC_CTRL_2_WORD_WIDTH_24_BITS (0 << 3)
#define AD1937_DAC_CTRL_2_WORD_WIDTH_20_BITS (1 << 3)
#define AD1937_DAC_CTRL_2_WORD_WIDTH_16_BITS (3 << 3)
#define AD1937_DAC_CTRL_2_DAC_OUTPUT_POLARITY_MASK (1 << 5)
#define AD1937_DAC_CTRL_2_DAC_OUTPUT_POLARITY_NORMAL (0 << 5)
#define AD1937_DAC_CTRL_2_DAC_OUTPUT_POLARITY_INVERTED (1 << 5)
#define AD1937_DAC_MUTE_CTRL_DAC1L_MASK (1 << 0)
#define AD1937_DAC_MUTE_CTRL_DAC1L_UNMUTE (0 << 0)
#define AD1937_DAC_MUTE_CTRL_DAC1L_MUTE (1 << 0)
#define AD1937_DAC_MUTE_CTRL_DAC1R_MASK (1 << 1)
#define AD1937_DAC_MUTE_CTRL_DAC1R_UNMUTE (0 << 1)
#define AD1937_DAC_MUTE_CTRL_DAC1R_MUTE (1 << 1)
#define AD1937_DAC_MUTE_CTRL_DAC2L_MASK (1 << 2)
#define AD1937_DAC_MUTE_CTRL_DAC2L_UNMUTE (0 << 2)
#define AD1937_DAC_MUTE_CTRL_DAC2L_MUTE (1 << 2)
#define AD1937_DAC_MUTE_CTRL_DAC2R_MASK (1 << 3)
#define AD1937_DAC_MUTE_CTRL_DAC2R_UNMUTE (0 << 3)
#define AD1937_DAC_MUTE_CTRL_DAC2R_MUTE (1 << 3)
#define AD1937_DAC_MUTE_CTRL_DAC3L_MASK (1 << 4)
#define AD1937_DAC_MUTE_CTRL_DAC3L_UNMUTE (0 << 4)
#define AD1937_DAC_MUTE_CTRL_DAC3L_MUTE (1 << 4)
#define AD1937_DAC_MUTE_CTRL_DAC3R_MASK (1 << 5)
#define AD1937_DAC_MUTE_CTRL_DAC3R_UNMUTE (0 << 5)
#define AD1937_DAC_MUTE_CTRL_DAC3R_MUTE (1 << 5)
#define AD1937_DAC_MUTE_CTRL_DAC4L_MASK (1 << 6)
#define AD1937_DAC_MUTE_CTRL_DAC4L_UNMUTE (0 << 6)
#define AD1937_DAC_MUTE_CTRL_DAC4L_MUTE (1 << 6)
#define AD1937_DAC_MUTE_CTRL_DAC4R_MASK (1 << 7)
#define AD1937_DAC_MUTE_CTRL_DAC4R_UNMUTE (0 << 7)
#define AD1937_DAC_MUTE_CTRL_DAC4R_MUTE (1 << 7)
#define AD1937_DAC_VOL_CTRL_DAC1L_MASK (0xff << 0)
#define AD1937_DAC_VOL_CTRL_DAC1R_MASK (0xff << 0)
#define AD1937_DAC_VOL_CTRL_DAC2L_MASK (0xff << 0)
#define AD1937_DAC_VOL_CTRL_DAC2R_MASK (0xff << 0)
#define AD1937_DAC_VOL_CTRL_DAC3L_MASK (0xff << 0)
#define AD1937_DAC_VOL_CTRL_DAC3R_MASK (0xff << 0)
#define AD1937_DAC_VOL_CTRL_DAC4L_MASK (0xff << 0)
#define AD1937_DAC_VOL_CTRL_DAC4R_MASK (0xff << 0)
#define AD1937_ADC_CTRL_0_PWR_MASK (1 << 0)
#define AD1937_ADC_CTRL_0_PWR_ON (0 << 0)
#define AD1937_ADC_CTRL_0_PWR_OFF (1 << 0)
#define AD1937_ADC_CTRL_0_HIGH_PASS_FILTER_MASK (1 << 1)
#define AD1937_ADC_CTRL_0_HIGH_PASS_FILTER_OFF (0 << 1)
#define AD1937_ADC_CTRL_0_HIGH_PASS_FILTER_ON (1 << 1)
#define AD1937_ADC_CTRL_0_ADC1L_MASK (1 << 2)
#define AD1937_ADC_CTRL_0_ADC1L_UNMUTE (0 << 2)
#define AD1937_ADC_CTRL_0_ADC1L_MUTE (1 << 2)
#define AD1937_ADC_CTRL_0_ADC1R_MASK (1 << 3)
#define AD1937_ADC_CTRL_0_ADC1R_UNMUTE (0 << 3)
#define AD1937_ADC_CTRL_0_ADC1R_MUTE (1 << 3)
#define AD1937_ADC_CTRL_0_ADC2L_MASK (1 << 4)
#define AD1937_ADC_CTRL_0_ADC2L_UNMUTE (0 << 4)
#define AD1937_ADC_CTRL_0_ADC2L_MUTE (1 << 4)
#define AD1937_ADC_CTRL_0_ADC2R_MASK (1 << 5)
#define AD1937_ADC_CTRL_0_ADC2R_UNMUTE (0 << 5)
#define AD1937_ADC_CTRL_0_ADC2R_MUTE (1 << 5)
#define AD1937_ADC_CTRL_0_SAMPLE_RATE_MASK (3 << 6)
#define AD1937_ADC_CTRL_0_SAMPLE_RATE_32_44_1_48_KHZ (0 << 6)
#define AD1937_ADC_CTRL_0_SAMPLE_RATE_64_88_2_96_KHZ (1 << 6)
#define AD1937_ADC_CTRL_0_SAMPLE_RATE_128_176_4_192_KHZ (2 << 6)
#define AD1937_ADC_CTRL_1_WORD_WIDTH_MASK (3 << 0)
#define AD1937_ADC_CTRL_1_WORD_WIDTH_24_BITS (0 << 0)
#define AD1937_ADC_CTRL_1_WORD_WIDTH_20_BITS (1 << 0)
#define AD1937_ADC_CTRL_1_WORD_WIDTH_16_BITS (3 << 0)
#define AD1937_ADC_CTRL_1_ASDATA_DELAY_MASK (7 << 2)
#define AD1937_ADC_CTRL_1_ASDATA_DELAY_1 (0 << 2)
#define AD1937_ADC_CTRL_1_ASDATA_DELAY_0 (1 << 2)
#define AD1937_ADC_CTRL_1_ASDATA_DELAY_8 (2 << 2)
#define AD1937_ADC_CTRL_1_ASDATA_DELAY_12 (3 << 2)
#define AD1937_ADC_CTRL_1_ASDATA_DELAY_16 (4 << 2)
#define AD1937_ADC_CTRL_1_FMT_MASK (3 << 5)
#define AD1937_ADC_CTRL_1_FMT_STEREO (0 << 5)
#define AD1937_ADC_CTRL_1_FMT_TDM_SINGLE_LINE (1 << 5)
#define AD1937_ADC_CTRL_1_FMT_TDM_AUX (2 << 5)
#define AD1937_ADC_CTRL_1_ABCLK_ACTIVE_EDGE_MASK (1 << 7)
#define AD1937_ADC_CTRL_1_ABCLK_ACTIVE_EDGE_MIDCYCLE (0 << 7)
#define AD1937_ADC_CTRL_1_ABCLK_ACTIVE_EDGE_PIPELINE (1 << 7)
#define AD1937_ADC_CTRL_2_ALRCLK_FMT_MASK (1 << 0)
#define AD1937_ADC_CTRL_2_ALRCLK_FMT_50_50 (0 << 0)
#define AD1937_ADC_CTRL_2_ALRCLK_FMT_PULSE (1 << 0)
#define AD1937_ADC_CTRL_2_ABCLK_POLARITY_MASK (1 << 1)
#define AD1937_ADC_CTRL_2_ABCLK_POLARITY_FALLING_EDGE (0 << 1)
#define AD1937_ADC_CTRL_2_ABCLK_POLARITY_RISING_EDGE (1 << 1)
#define AD1937_ADC_CTRL_2_ALRCLK_POLARITY_MASK (1 << 2)
#define AD1937_ADC_CTRL_2_ALRCLK_POLARITY_LEFT_LOW (0 << 2)
#define AD1937_ADC_CTRL_2_ALRCLK_POLARITY_LEFT_HIGH (1 << 2)
#define AD1937_ADC_CTRL_2_ALRCLK_MASK (1 << 3)
#define AD1937_ADC_CTRL_2_ALRCLK_SLAVE (0 << 3)
#define AD1937_ADC_CTRL_2_ALRCLK_MASTER (1 << 3)
#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_MASK (3 << 4)
#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_64 (0 << 4)
#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_128 (1 << 4)
#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_256 (2 << 4)
#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_512 (3 << 4)
#define AD1937_ADC_CTRL_2_ABCLK_MASK (1 << 6)
#define AD1937_ADC_CTRL_2_ABCLK_SLAVE (0 << 6)
#define AD1937_ADC_CTRL_2_ABCLK_MASTER (1 << 6)
#define AD1937_ADC_CTRL_2_ABCLK_SOURCE_MASK (1 << 7)
#define AD1937_ADC_CTRL_2_ABCLK_SOURCE_ABCLK_PIN (0 << 7)
#define AD1937_ADC_CTRL_2_ABCLK_SOURCE_INTERNAL (1 << 7)
#define AUDIO_CODEC_SLAVE_MODE 1
#define AUDIO_CODEC_MASTER_MODE 0
#define AUDIO_DAC_MASTER_MODE 1
#define AUDIO_DAC_SLAVE_MODE 0
#define I2S_DATAWIDTH_04 0
#define I2S_DATAWIDTH_08 1
#define I2S_DATAWIDTH_12 2
#define I2S_DATAWIDTH_16 3
#define I2S_DATAWIDTH_20 4
#define I2S_DATAWIDTH_24 5
#define I2S_DATAWIDTH_28 6
#define I2S_DATAWIDTH_32 7
#define AD1937_MCLK_PLL_INTERNAL_MODE 0
#define AD1937_MCLK_DIRECT_MODE 1
enum AUDIO_INTERFACE_FORMAT{
AUDIO_INTERFACE_I2S_FORMAT,
AUDIO_INTERFACE_LJM_FORMAT,
AUDIO_INTERFACE_RJM_FORMAT,
AUDIO_INTERFACE_DSP_FORMAT,
AUDIO_INTERFACE_PCM_FORMAT,
AUDIO_INTERFACE_NW_FORMAT,
AUDIO_INTERFACE_TDM_FORMAT,
AUDIO_INTERFACE_TOTAL_FORMAT
};
typedef struct AD1937_EXTRA_INFO{
unsigned int codecId;
unsigned int clkgenId;
unsigned int dacMasterEn;
unsigned int daisyEn;
unsigned int mclk_mode;
} AD1937_EXTRA_INFO;
struct ahub_unit_fpga {
unsigned int configured;
void __iomem *ape_fpga_misc_base;
void __iomem *ape_fpga_misc_i2s_clk_base[5];
void __iomem *ape_i2c_base;
void __iomem *pinmux_base;
void __iomem *ape_gpio_base;
void __iomem *rst_clk_base;
void __iomem *i2s5_cya_base;
};
void i2c_write(u32 addr, u32 regAddrr, u32 regData, u32 NoBytes);
u32 i2c_read(u32 addr, u32 regAddrr);
void i2s_clk_divider(u32 i2s, u32 Divider);
void i2c_clk_divider(u32 Divider);
void program_max_codec(void);
void program_cdc_pll(u32 PLLno, u32 Freq);
void i2s_clk_setup(u32 i2s, u32 source, u32 divider);
void i2c_pinmux_setup(void);
void i2c_clk_setup(u32 divider);
void i2s_pinmux_setup(u32 i2s, u32 i2s_b);
void program_io_expander(void);
void program_dmic_gpio(void);
void program_dmic_clk(int dmic_clk);
void SetMax9485(int freq);
void ahub_unit_fpga_init_t210(void);
void ahub_unit_fpga_init_t186(void);
void ahub_unit_fpga_deinit(void);
struct ahub_unit_fpga *get_ahub_unit_fpga_private(void);
void program_dspk_clk(int dspk_clk);
void OnAD1937CaptureAndPlayback(int mode,
int codec_data_format,
int codec_data_width,
int bitSize,
int polarity,
int bitclkInv,
int frameRate,
AD1937_EXTRA_INFO * extra_info);
#endif

78
sound/soc/tegra-alt/include/tegra_asoc_utils_alt.h
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@@ -1,78 +0,0 @@
/*
* tegra_alt_asoc_utils.h - Definitions for MCLK and DAP Utility driver
*
* Author: Stephen Warren <swarren@nvidia.com>
* Copyright (c) 2011-2019 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __TEGRA_ASOC_UTILS_ALT_H_
#define __TEGRA_ASOC_UTILS_ALT_H_
struct clk;
struct device;
enum tegra_asoc_utils_soc {
TEGRA_ASOC_UTILS_SOC_TEGRA210,
TEGRA_ASOC_UTILS_SOC_TEGRA186,
TEGRA_ASOC_UTILS_SOC_TEGRA194,
};
/*
* Maintain same order in DT entry
* FIXME: (This would be removed going ahead)
*/
enum tegra_asoc_utils_clkrate {
PLLA_x11025_RATE,
AUD_MCLK_x11025_RATE,
PLLA_OUT0_x11025_RATE,
AHUB_x11025_RATE,
PLLA_x8000_RATE,
AUD_MCLK_x8000_RATE,
PLLA_OUT0_x8000_RATE,
AHUB_x8000_RATE,
MAX_NUM_RATES,
};
struct tegra_asoc_audio_clock_info {
struct device *dev;
struct snd_soc_card *card;
enum tegra_asoc_utils_soc soc;
struct clk *clk_pll_base;
struct clk *clk_pll_out;
struct clk *clk_aud_mclk;
struct reset_control *clk_cdev1_rst;
unsigned int *pll_base_rate;
u32 set_pll_base_rate;
u32 set_pll_out_rate;
u32 set_aud_mclk_rate;
u32 mclk_scale;
/* FIXME: below would be removed going ahead */
u32 clk_rates[MAX_NUM_RATES];
u32 num_clk;
};
int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
unsigned int srate, unsigned int mclk,
unsigned int clk_out_rate);
int tegra_alt_asoc_utils_init(struct tegra_asoc_audio_clock_info *data,
struct device *dev, struct snd_soc_card *card);
int tegra_alt_asoc_utils_clk_enable(struct tegra_asoc_audio_clock_info *data);
int tegra_alt_asoc_utils_clk_disable(struct tegra_asoc_audio_clock_info *data);
#endif

47
sound/soc/tegra-alt/include/tegra_pcm_alt.h
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@@ -1,47 +0,0 @@
/*
* tegra_pcm_alt.h - Definitions for Tegra PCM driver
*
* Author: Stephen Warren <swarren@nvidia.com>
* Copyright (c) 2011-2019 NVIDIA CORPORATION. All rights reserved.
*
* Based on code copyright/by:
*
* Copyright (c) 2009-2010, NVIDIA Corporation.
* Scott Peterson <speterson@nvidia.com>
*
* Copyright (C) 2010 Google, Inc.
* Iliyan Malchev <malchev@google.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __TEGRA_PCM_ALT_H__
#define __TEGRA_PCM_ALT_H__
#define MAX_DMA_REQ_COUNT 2
struct tegra_alt_pcm_dma_params {
unsigned long addr;
unsigned long width;
unsigned long req_sel;
const char *chan_name;
size_t buffer_size;
};
int tegra_alt_pcm_platform_register(struct device *dev);
void tegra_alt_pcm_platform_unregister(struct device *dev);
#endif

1424
sound/soc/tegra-alt/utils/ahub_unit_fpga_clock.c
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208
sound/soc/tegra-alt/utils/tegra_asoc_utils_alt.c
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@@ -1,208 +0,0 @@
/*
* tegra_asoc_utils_alt.c - MCLK and DAP Utility driver
*
* Author: Stephen Warren <swarren@nvidia.com>
* Copyright (c) 2010-2019 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk/tegra.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include "tegra_asoc_utils_alt.h"
enum rate_type {
ODD_RATE,
EVEN_RATE,
NUM_RATE_TYPE,
};
unsigned int tegra210_pll_base_rate[NUM_RATE_TYPE] = {
338688000,
368640000,
};
unsigned int tegra186_pll_base_rate[NUM_RATE_TYPE] = {
270950400,
245760000,
};
unsigned int default_pll_out_rate[NUM_RATE_TYPE] = {
45158400,
49152000,
};
int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
unsigned int srate, unsigned int pll_out,
unsigned int aud_mclk)
{
unsigned int new_pll_base;
int err;
switch (srate) {
case 11025:
case 22050:
case 44100:
case 88200:
case 176400:
new_pll_base = data->pll_base_rate[ODD_RATE];
pll_out = default_pll_out_rate[ODD_RATE];
break;
case 8000:
case 16000:
case 32000:
case 48000:
case 64000:
case 96000:
case 192000:
new_pll_base = data->pll_base_rate[EVEN_RATE];
pll_out = default_pll_out_rate[EVEN_RATE];
break;
default:
return -EINVAL;
}
/* reduce pll_out rate to support lower sampling rates */
if (srate <= 11025)
pll_out = pll_out >> 1;
if (data->mclk_scale)
aud_mclk = srate * data->mclk_scale;
if (data->set_pll_base_rate != new_pll_base) {
err = clk_set_rate(data->clk_pll_base, new_pll_base);
if (err) {
dev_err(data->dev, "Can't set clk_pll_base rate: %d\n",
err);
return err;
}
data->set_pll_base_rate = new_pll_base;
}
if (data->set_pll_out_rate != pll_out) {
err = clk_set_rate(data->clk_pll_out, pll_out);
if (err) {
dev_err(data->dev, "Can't set clk_pll_out rate: %d\n",
err);
return err;
}
data->set_pll_out_rate = pll_out;
}
if (data->set_aud_mclk_rate != aud_mclk) {
err = clk_set_rate(data->clk_aud_mclk, aud_mclk);
if (err) {
dev_err(data->dev, "Can't set clk_cdev1 rate: %d\n",
err);
return err;
}
data->set_aud_mclk_rate = aud_mclk;
}
return 0;
}
EXPORT_SYMBOL_GPL(tegra_alt_asoc_utils_set_rate);
int tegra_alt_asoc_utils_clk_enable(struct tegra_asoc_audio_clock_info *data)
{
int err;
if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA186)
reset_control_reset(data->clk_cdev1_rst);
err = clk_prepare_enable(data->clk_aud_mclk);
if (err) {
dev_err(data->dev, "Can't enable cdev1: %d\n", err);
return err;
}
return 0;
}
EXPORT_SYMBOL_GPL(tegra_alt_asoc_utils_clk_enable);
int tegra_alt_asoc_utils_clk_disable(struct tegra_asoc_audio_clock_info *data)
{
clk_disable_unprepare(data->clk_aud_mclk);
return 0;
}
EXPORT_SYMBOL_GPL(tegra_alt_asoc_utils_clk_disable);
int tegra_alt_asoc_utils_init(struct tegra_asoc_audio_clock_info *data,
struct device *dev, struct snd_soc_card *card)
{
data->dev = dev;
data->card = card;
if (of_machine_is_compatible("nvidia,tegra210") ||
of_machine_is_compatible("nvidia,tegra210b01"))
data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA210;
else if (of_machine_is_compatible("nvidia,tegra186"))
data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA186;
else if (of_machine_is_compatible("nvidia,tegra194"))
data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA194;
else
/* DT boot, but unknown SoC */
return -EINVAL;
data->clk_pll_base = devm_clk_get(dev, "pll_a");
if (IS_ERR(data->clk_pll_base)) {
dev_err(data->dev, "Can't retrieve clk pll_a\n");
return PTR_ERR(data->clk_pll_base);
}
data->clk_pll_out = devm_clk_get(dev, "pll_a_out0");
if (IS_ERR(data->clk_pll_out)) {
dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
return PTR_ERR(data->clk_pll_out);
}
data->clk_aud_mclk = devm_clk_get(dev, "extern1");
if (IS_ERR(data->clk_aud_mclk)) {
dev_err(data->dev, "Can't retrieve clk cdev1\n");
return PTR_ERR(data->clk_aud_mclk);
}
if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA186) {
data->clk_cdev1_rst = devm_reset_control_get(dev,
"extern1_rst");
if (IS_ERR(data->clk_cdev1_rst)) {
dev_err(dev, "Reset control is not found, err: %ld\n",
PTR_ERR(data->clk_cdev1_rst));
return PTR_ERR(data->clk_cdev1_rst);
}
reset_control_reset(data->clk_cdev1_rst);
}
if (data->soc < TEGRA_ASOC_UTILS_SOC_TEGRA186)
data->pll_base_rate = tegra210_pll_base_rate;
else
data->pll_base_rate = tegra186_pll_base_rate;
return 0;
}
EXPORT_SYMBOL_GPL(tegra_alt_asoc_utils_init);
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra ASoC utility code");
MODULE_LICENSE("GPL");

354
sound/soc/tegra-alt/utils/tegra_pcm_alt.c
View File

@@ -1,354 +0,0 @@
/*
* tegra_alt_pcm.c - Tegra PCM driver
*
* Author: Stephen Warren <swarren@nvidia.com>
* Copyright (c) 2011-2019 NVIDIA CORPORATION. All rights reserved.
*
* Based on code copyright/by:
*
* Copyright (c) 2009-2010, NVIDIA Corporation.
* Scott Peterson <speterson@nvidia.com>
* Vijay Mali <vmali@nvidia.com>
*
* Copyright (C) 2010 Google, Inc.
* Iliyan Malchev <malchev@google.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "tegra_pcm_alt.h"
static const struct snd_pcm_hardware tegra_alt_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_INTERLEAVED,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S32_LE,
.period_bytes_min = 128,
.period_bytes_max = PAGE_SIZE * 4,
.periods_min = 1,
.periods_max = 8,
.buffer_bytes_max = PAGE_SIZE * 8,
.fifo_size = 4,
};
static int tegra_alt_pcm_open(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct tegra_alt_pcm_dma_params *dmap;
int ret;
if (rtd->dai_link->no_pcm)
return 0;
dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
/* Set HW params now that initialization is complete */
snd_soc_set_runtime_hwparams(substream, &tegra_alt_pcm_hardware);
/* Update buffer size from device tree */
if (dmap->buffer_size > substream->runtime->hw.buffer_bytes_max) {
substream->runtime->hw.buffer_bytes_max = dmap->buffer_size;
substream->runtime->hw.period_bytes_max = dmap->buffer_size / 2;
}
/* Ensure period size is multiple of 8 */
ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 0x8);
if (ret) {
dev_err(dev, "failed to set constraint %d\n", ret);
return ret;
}
ret = snd_dmaengine_pcm_open(substream,
dma_request_slave_channel(dev, dmap->chan_name));
if (ret) {
dev_err(dev, "dmaengine pcm open failed with err %d\n", ret);
return ret;
}
return 0;
}
static int tegra_alt_pcm_close(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
if (rtd->dai_link->no_pcm)
return 0;
snd_dmaengine_pcm_close_release_chan(substream);
return 0;
}
static int tegra_alt_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct dma_chan *chan;
struct tegra_alt_pcm_dma_params *dmap;
struct dma_slave_config slave_config;
int ret;
if (rtd->dai_link->no_pcm)
return 0;
dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
if (!dmap)
return 0;
chan = snd_dmaengine_pcm_get_chan(substream);
ret = snd_hwparams_to_dma_slave_config(substream, params,
&slave_config);
if (ret) {
dev_err(dev, "hw params config failed with err %d\n", ret);
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
slave_config.dst_addr = dmap->addr;
slave_config.dst_maxburst = 8;
} else {
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
slave_config.src_addr = dmap->addr;
slave_config.src_maxburst = 8;
}
slave_config.slave_id = dmap->req_sel;
ret = dmaengine_slave_config(chan, &slave_config);
if (ret < 0) {
dev_err(dev, "dma slave config failed with err %d\n", ret);
return ret;
}
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
return 0;
}
static int tegra_alt_pcm_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
if (rtd->dai_link->no_pcm)
return 0;
snd_pcm_set_runtime_buffer(substream, NULL);
return 0;
}
static int tegra_alt_pcm_mmap(struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
if (rtd->dai_link->no_pcm)
return 0;
return dma_mmap_writecombine(substream->pcm->card->dev, vma,
runtime->dma_area,
runtime->dma_addr,
runtime->dma_bytes);
}
static snd_pcm_uframes_t tegra_alt_pcm_pointer
(struct snd_pcm_substream *substream)
{
snd_pcm_uframes_t appl_offset, pos = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
char *appl_ptr;
pos = snd_dmaengine_pcm_pointer(substream);
/* In DRAINING state pointer callback comes from dma completion, here
* we want to make sure if if dma completion callback is late we should
* not endup playing stale data.
*/
if ((runtime->status->state == SNDRV_PCM_STATE_DRAINING) &&
(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) {
appl_offset = runtime->control->appl_ptr %
runtime->buffer_size;
appl_ptr = runtime->dma_area + frames_to_bytes(runtime,
appl_offset);
if (pos < appl_offset) {
memset(appl_ptr, 0, frames_to_bytes(runtime,
runtime->buffer_size - appl_offset));
memset(runtime->dma_area, 0, frames_to_bytes(runtime,
pos));
} else
memset(appl_ptr, 0, frames_to_bytes(runtime,
pos - appl_offset));
}
return pos;
}
static struct snd_pcm_ops tegra_alt_pcm_ops = {
.open = tegra_alt_pcm_open,
.close = tegra_alt_pcm_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = tegra_alt_pcm_hw_params,
.hw_free = tegra_alt_pcm_hw_free,
.trigger = snd_dmaengine_pcm_trigger,
.pointer = tegra_alt_pcm_pointer,
.mmap = tegra_alt_pcm_mmap,
};
static int tegra_alt_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,
int stream , size_t size)
{
struct snd_pcm_substream *substream = pcm->streams[stream].substream;
struct snd_dma_buffer *buf = &substream->dma_buffer;
buf->area = dma_alloc_coherent(pcm->card->dev, size,
&buf->addr, GFP_KERNEL);
if (!buf->area)
return -ENOMEM;
buf->private_data = NULL;
buf->dev.type = SNDRV_DMA_TYPE_DEV;
buf->dev.dev = pcm->card->dev;
buf->bytes = size;
return 0;
}
static void tegra_alt_pcm_deallocate_dma_buffer(struct snd_pcm *pcm, int stream)
{
struct snd_pcm_substream *substream;
struct snd_dma_buffer *buf;
substream = pcm->streams[stream].substream;
if (!substream)
return;
buf = &substream->dma_buffer;
if (!buf->area)
return;
dma_free_coherent(pcm->card->dev, buf->bytes,
buf->area, buf->addr);
buf->area = NULL;
}
#if defined(CONFIG_ARCH_TEGRA_APE)
static u64 tegra_dma_mask = DMA_BIT_MASK(64);
#else
static u64 tegra_dma_mask = DMA_BIT_MASK(32);
#endif
static int tegra_alt_pcm_dma_allocate(struct snd_soc_pcm_runtime *rtd,
size_t size)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
struct tegra_alt_pcm_dma_params *dmap;
size_t buffer_size = size;
int ret = 0;
if (!card->dev->dma_mask)
card->dev->dma_mask = &tegra_dma_mask;
if (!card->dev->coherent_dma_mask)
card->dev->coherent_dma_mask = tegra_dma_mask;
dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai,
pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
if (dmap->buffer_size > size)
buffer_size = dmap->buffer_size;
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
ret = tegra_alt_pcm_preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_PLAYBACK,
buffer_size);
if (ret)
goto err;
}
dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai,
pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
if (dmap->buffer_size > size)
buffer_size = dmap->buffer_size;
if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
ret = tegra_alt_pcm_preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_CAPTURE,
buffer_size);
if (ret)
goto err_free_play;
}
return 0;
err_free_play:
tegra_alt_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
err:
return ret;
}
static int tegra_alt_pcm_new(struct snd_soc_pcm_runtime *rtd)
{
return tegra_alt_pcm_dma_allocate(rtd,
tegra_alt_pcm_hardware.buffer_bytes_max);
}
static void tegra_alt_pcm_free(struct snd_pcm *pcm)
{
tegra_alt_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_CAPTURE);
tegra_alt_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
}
static int tegra_alt_pcm_probe(struct snd_soc_platform *platform)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(&platform->component);
dapm->idle_bias_off = 1;
return 0;
}
static struct snd_soc_platform_driver tegra_alt_pcm_platform = {
.ops = &tegra_alt_pcm_ops,
.pcm_new = tegra_alt_pcm_new,
.pcm_free = tegra_alt_pcm_free,
.probe = tegra_alt_pcm_probe,
};
int tegra_alt_pcm_platform_register(struct device *dev)
{
return snd_soc_register_platform(dev, &tegra_alt_pcm_platform);
}
EXPORT_SYMBOL_GPL(tegra_alt_pcm_platform_register);
void tegra_alt_pcm_platform_unregister(struct device *dev)
{
snd_soc_unregister_platform(dev);
}
EXPORT_SYMBOL_GPL(tegra_alt_pcm_platform_unregister);
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra Alt PCM ASoC driver");
MODULE_LICENSE("GPL");