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drm/tegra: Export active signal to actmon

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As long as the subcomponents in the engine are active, we consider the
engine as active and the engine should export active signal to the
actmon.

Bug 4179140

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Change-Id: Ic4cccf29e8ac87da24f6fe3bf1f1e93a11511762
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2930445
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Johnny Liu
2023-07-04 03:02:15 +00:00
committed by mobile promotions
parent 38c963de57
commit 4241a7c976
5 changed files with 92 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/gpu/drm/tegra/nvdec.c
View File

@@ -3,6 +3,7 @@
* Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. * Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
*/ */
#include <linux/bitops.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/devfreq.h> #include <linux/devfreq.h>
@@ -29,14 +30,23 @@
#include "riscv.h" #include "riscv.h"
#include "util.h" #include "util.h"
#define NVDEC_FW_MTHD_ADDR_ACTMON_WEIGHT 0xC9U #define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_MASK 0xCAU
#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_BORPS 0xCBU
#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_WEIGHT 0xC9U
#define NVDEC_FALCON_UCLASS_METHOD_OFFSET 0x40 #define NVDEC_FALCON_UCLASS_METHOD_OFFSET 0x40
#define NVDEC_FALCON_UCLASS_METHOD_DATA 0x44 #define NVDEC_FALCON_UCLASS_METHOD_DATA 0x44
#define NVDEC_FALCON_DEBUGINFO 0x1094 #define NVDEC_FALCON_DEBUGINFO 0x1094
#define NVDEC_TFBIF_TRANSCFG 0x2c44 #define NVDEC_TFBIF_TRANSCFG 0x2c44
#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK 0x2c4c
#define NVDEC_TFBIF_ACTMON_ACTIVE_BORPS 0x2c50
#define NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x2c54 #define NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x2c54
#define NVDEC_AXI_RW_BANDWIDTH 512 #define NVDEC_AXI_RW_BANDWIDTH 512
#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
#define NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
struct nvdec_config { struct nvdec_config {
const char *firmware; const char *firmware;
unsigned int version; unsigned int version;
@@ -109,7 +119,7 @@ static int nvdec_set_rate(struct nvdec *nvdec, unsigned long rate)
nvdec_writel(nvdec, weight, NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT); nvdec_writel(nvdec, weight, NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT);
} else { } else {
nvdec_writel(nvdec, nvdec_writel(nvdec,
NVDEC_FW_MTHD_ADDR_ACTMON_WEIGHT, NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_WEIGHT,
NVDEC_FALCON_UCLASS_METHOD_OFFSET); NVDEC_FALCON_UCLASS_METHOD_OFFSET);
nvdec_writel(nvdec, weight, NVDEC_FALCON_UCLASS_METHOD_DATA); nvdec_writel(nvdec, weight, NVDEC_FALCON_UCLASS_METHOD_DATA);
} }
@@ -523,6 +533,22 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev)
err = nvdec_boot_riscv(nvdec); err = nvdec_boot_riscv(nvdec);
if (err < 0) if (err < 0)
goto disable; goto disable;
nvdec_writel(nvdec,
NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_MASK,
NVDEC_FALCON_UCLASS_METHOD_OFFSET);
nvdec_writel(nvdec,
NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED |
NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED,
NVDEC_FALCON_UCLASS_METHOD_DATA);
nvdec_writel(nvdec,
NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_BORPS,
NVDEC_FALCON_UCLASS_METHOD_OFFSET);
nvdec_writel(nvdec,
NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
NVDEC_FALCON_UCLASS_METHOD_DATA);
} else { } else {
err = nvdec_load_falcon_firmware(nvdec); err = nvdec_load_falcon_firmware(nvdec);
if (err < 0) if (err < 0)
@@ -531,6 +557,16 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev)
err = nvdec_boot_falcon(nvdec); err = nvdec_boot_falcon(nvdec);
if (err < 0) if (err < 0)
goto disable; goto disable;
nvdec_writel(nvdec,
NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED |
NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED,
NVDEC_TFBIF_ACTMON_ACTIVE_MASK);
nvdec_writel(nvdec,
NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
NVDEC_TFBIF_ACTMON_ACTIVE_BORPS);
} }
devfreq_resume_device(nvdec->devfreq); devfreq_resume_device(nvdec->devfreq);

18
drivers/gpu/drm/tegra/nvenc.c
View File

@@ -3,6 +3,7 @@
* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
*/ */
#include <linux/bitops.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/devfreq.h> #include <linux/devfreq.h>
@@ -27,9 +28,16 @@
#include "util.h" #include "util.h"
#define NVENC_TFBIF_TRANSCFG 0x1844 #define NVENC_TFBIF_TRANSCFG 0x1844
#define NVENC_TFBIF_ACTMON_ACTIVE_MASK 0x184c
#define NVENC_TFBIF_ACTMON_ACTIVE_BORPS 0x1850
#define NVENC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1854 #define NVENC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1854
#define NVENC_AXI_RW_BANDWIDTH 512 #define NVENC_AXI_RW_BANDWIDTH 512
#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
#define NVENC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
struct nvenc_config { struct nvenc_config {
const char *firmware; const char *firmware;
unsigned int version; unsigned int version;
@@ -444,6 +452,16 @@ static __maybe_unused int nvenc_runtime_resume(struct device *dev)
if (err < 0) if (err < 0)
goto disable; goto disable;
nvenc_writel(nvenc,
NVENC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED |
NVENC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
NVENC_TFBIF_ACTMON_ACTIVE_MASK_STARVED,
NVENC_TFBIF_ACTMON_ACTIVE_MASK);
nvenc_writel(nvenc,
NVENC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
NVENC_TFBIF_ACTMON_ACTIVE_BORPS);
devfreq_resume_device(nvenc->devfreq); devfreq_resume_device(nvenc->devfreq);
return 0; return 0;

18
drivers/gpu/drm/tegra/nvjpg.c
View File

@@ -3,6 +3,7 @@
* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
*/ */
#include <linux/bitops.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/devfreq.h> #include <linux/devfreq.h>
@@ -27,9 +28,16 @@
#include "util.h" #include "util.h"
#define NVJPG_TFBIF_TRANSCFG 0x1444 #define NVJPG_TFBIF_TRANSCFG 0x1444
#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK 0x144c
#define NVJPG_TFBIF_ACTMON_ACTIVE_BORPS 0x1450
#define NVJPG_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1454 #define NVJPG_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1454
#define NVJPG_AXI_RW_BANDWIDTH 512 #define NVJPG_AXI_RW_BANDWIDTH 512
#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
#define NVJPG_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
struct nvjpg_config { struct nvjpg_config {
const char *firmware; const char *firmware;
unsigned int version; unsigned int version;
@@ -443,6 +451,16 @@ static __maybe_unused int nvjpg_runtime_resume(struct device *dev)
if (err < 0) if (err < 0)
goto disable; goto disable;
nvjpg_writel(nvjpg,
NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STARVED |
NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
NVJPG_TFBIF_ACTMON_ACTIVE_MASK_DELAYED,
NVJPG_TFBIF_ACTMON_ACTIVE_MASK);
nvjpg_writel(nvjpg,
NVJPG_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
NVJPG_TFBIF_ACTMON_ACTIVE_BORPS);
devfreq_resume_device(nvjpg->devfreq); devfreq_resume_device(nvjpg->devfreq);
return 0; return 0;

11
drivers/gpu/drm/tegra/vic.c
View File

@@ -3,6 +3,7 @@
* Copyright (C) 2015-2023 NVIDIA CORPORATION. All rights reserved. * Copyright (C) 2015-2023 NVIDIA CORPORATION. All rights reserved.
*/ */
#include <linux/bitops.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/devfreq.h> #include <linux/devfreq.h>
@@ -507,6 +508,16 @@ static int __maybe_unused vic_runtime_resume(struct device *dev)
if (err < 0) if (err < 0)
goto assert; goto assert;
vic_writel(vic,
VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED |
VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED,
NV_PVIC_TFBIF_ACTMON_ACTIVE_MASK);
vic_writel(vic,
VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
NV_PVIC_TFBIF_ACTMON_ACTIVE_BORPS);
devfreq_resume_device(vic->devfreq); devfreq_resume_device(vic->devfreq);
return 0; return 0;

7
drivers/gpu/drm/tegra/vic.h
View File

@@ -18,8 +18,15 @@
#define CG_IDLE_CG_EN (1 << 6) #define CG_IDLE_CG_EN (1 << 6)
#define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
#define NV_PVIC_TFBIF_ACTMON_ACTIVE_MASK 0x0000204c
#define NV_PVIC_TFBIF_ACTMON_ACTIVE_BORPS 0x00002050
#define NV_PVIC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x00002054 #define NV_PVIC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x00002054
#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
#define VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
#define VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
#define VIC_TFBIF_TRANSCFG 0x00002044 #define VIC_TFBIF_TRANSCFG 0x00002044
/* Firmware offsets */ /* Firmware offsets */