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drm/tegra: Export active signal to actmon
As long as the subcomponents in the engine are active, we consider the engine as active and the engine should export active signal to the actmon. Bug 4179140 Signed-off-by: Johnny Liu <johnliu@nvidia.com> Change-Id: Ic4cccf29e8ac87da24f6fe3bf1f1e93a11511762 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2930445 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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Johnny Liu
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@@ -3,6 +3,7 @@
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* Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/devfreq.h>
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@@ -29,14 +30,23 @@
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#include "riscv.h"
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#include "util.h"
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#define NVDEC_FW_MTHD_ADDR_ACTMON_WEIGHT 0xC9U
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#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_MASK 0xCAU
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#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_BORPS 0xCBU
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#define NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_WEIGHT 0xC9U
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#define NVDEC_FALCON_UCLASS_METHOD_OFFSET 0x40
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#define NVDEC_FALCON_UCLASS_METHOD_DATA 0x44
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#define NVDEC_FALCON_DEBUGINFO 0x1094
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#define NVDEC_TFBIF_TRANSCFG 0x2c44
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#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK 0x2c4c
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#define NVDEC_TFBIF_ACTMON_ACTIVE_BORPS 0x2c50
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#define NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x2c54
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#define NVDEC_AXI_RW_BANDWIDTH 512
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#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
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#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
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#define NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
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#define NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
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struct nvdec_config {
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const char *firmware;
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unsigned int version;
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@@ -109,7 +119,7 @@ static int nvdec_set_rate(struct nvdec *nvdec, unsigned long rate)
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nvdec_writel(nvdec, weight, NVDEC_TFBIF_ACTMON_ACTIVE_WEIGHT);
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} else {
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nvdec_writel(nvdec,
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NVDEC_FW_MTHD_ADDR_ACTMON_WEIGHT,
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NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_WEIGHT,
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NVDEC_FALCON_UCLASS_METHOD_OFFSET);
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nvdec_writel(nvdec, weight, NVDEC_FALCON_UCLASS_METHOD_DATA);
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}
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@@ -523,6 +533,22 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev)
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err = nvdec_boot_riscv(nvdec);
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if (err < 0)
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goto disable;
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nvdec_writel(nvdec,
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NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_MASK,
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NVDEC_FALCON_UCLASS_METHOD_OFFSET);
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nvdec_writel(nvdec,
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NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED |
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NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
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NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED,
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NVDEC_FALCON_UCLASS_METHOD_DATA);
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nvdec_writel(nvdec,
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NVDEC_FW_MTHD_ADDR_ACTMON_ACTIVE_BORPS,
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NVDEC_FALCON_UCLASS_METHOD_OFFSET);
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nvdec_writel(nvdec,
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NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
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NVDEC_FALCON_UCLASS_METHOD_DATA);
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} else {
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err = nvdec_load_falcon_firmware(nvdec);
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if (err < 0)
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@@ -531,6 +557,16 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev)
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err = nvdec_boot_falcon(nvdec);
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if (err < 0)
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goto disable;
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nvdec_writel(nvdec,
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NVDEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED |
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NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
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NVDEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED,
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NVDEC_TFBIF_ACTMON_ACTIVE_MASK);
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nvdec_writel(nvdec,
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NVDEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
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NVDEC_TFBIF_ACTMON_ACTIVE_BORPS);
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}
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devfreq_resume_device(nvdec->devfreq);
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@@ -3,6 +3,7 @@
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* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/devfreq.h>
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@@ -27,9 +28,16 @@
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#include "util.h"
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#define NVENC_TFBIF_TRANSCFG 0x1844
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#define NVENC_TFBIF_ACTMON_ACTIVE_MASK 0x184c
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#define NVENC_TFBIF_ACTMON_ACTIVE_BORPS 0x1850
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#define NVENC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1854
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#define NVENC_AXI_RW_BANDWIDTH 512
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#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
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#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
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#define NVENC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
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#define NVENC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
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struct nvenc_config {
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const char *firmware;
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unsigned int version;
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@@ -444,6 +452,16 @@ static __maybe_unused int nvenc_runtime_resume(struct device *dev)
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if (err < 0)
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goto disable;
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nvenc_writel(nvenc,
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NVENC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED |
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NVENC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
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NVENC_TFBIF_ACTMON_ACTIVE_MASK_STARVED,
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NVENC_TFBIF_ACTMON_ACTIVE_MASK);
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nvenc_writel(nvenc,
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NVENC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
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NVENC_TFBIF_ACTMON_ACTIVE_BORPS);
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devfreq_resume_device(nvenc->devfreq);
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return 0;
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@@ -3,6 +3,7 @@
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* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/devfreq.h>
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@@ -27,9 +28,16 @@
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#include "util.h"
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#define NVJPG_TFBIF_TRANSCFG 0x1444
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#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK 0x144c
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#define NVJPG_TFBIF_ACTMON_ACTIVE_BORPS 0x1450
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#define NVJPG_TFBIF_ACTMON_ACTIVE_WEIGHT 0x1454
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#define NVJPG_AXI_RW_BANDWIDTH 512
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#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
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#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
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#define NVJPG_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
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#define NVJPG_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
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struct nvjpg_config {
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const char *firmware;
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unsigned int version;
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@@ -443,6 +451,16 @@ static __maybe_unused int nvjpg_runtime_resume(struct device *dev)
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if (err < 0)
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goto disable;
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nvjpg_writel(nvjpg,
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NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STARVED |
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NVJPG_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
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NVJPG_TFBIF_ACTMON_ACTIVE_MASK_DELAYED,
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NVJPG_TFBIF_ACTMON_ACTIVE_MASK);
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nvjpg_writel(nvjpg,
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NVJPG_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
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NVJPG_TFBIF_ACTMON_ACTIVE_BORPS);
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devfreq_resume_device(nvjpg->devfreq);
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return 0;
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@@ -3,6 +3,7 @@
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* Copyright (C) 2015-2023 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/devfreq.h>
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@@ -507,6 +508,16 @@ static int __maybe_unused vic_runtime_resume(struct device *dev)
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if (err < 0)
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goto assert;
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vic_writel(vic,
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VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED |
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VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED |
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VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED,
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NV_PVIC_TFBIF_ACTMON_ACTIVE_MASK);
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vic_writel(vic,
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VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE,
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NV_PVIC_TFBIF_ACTMON_ACTIVE_BORPS);
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devfreq_resume_device(vic->devfreq);
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return 0;
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@@ -18,8 +18,15 @@
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#define CG_IDLE_CG_EN (1 << 6)
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#define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
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#define NV_PVIC_TFBIF_ACTMON_ACTIVE_MASK 0x0000204c
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#define NV_PVIC_TFBIF_ACTMON_ACTIVE_BORPS 0x00002050
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#define NV_PVIC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x00002054
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#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
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#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
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#define VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
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#define VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
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#define VIC_TFBIF_TRANSCFG 0x00002044
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/* Firmware offsets */
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