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nvethernet: eqos pad calibration reg offsets

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Make eqos pad calibration reg ETHER_QOS_AUTO_CAL_CONFIG_0 offsets
AUTO_CAL_PD_OFFSET and 	AUTO_CAL_PU_OFFSET configurable as per
customer boards tuning

Bug 3846183
Bug 4088361

Change-Id: I77521f83cac56650c6a6d1a2dd8b8c7cbdc3f3fc
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2806180
(cherry picked from commit 8eea133d313ba3b1b4ced9f58a65ecf870a2b0e6)
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2897231
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahesh Patil
2022-11-09 12:26:34 -08:00
committed by mobile promotions
parent d3bc17ca8b
commit 44419231b0
1 changed files with 40 additions and 0 deletions
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40
drivers/net/ethernet/nvidia/nvethernet/ether_linux.c
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@@ -5558,6 +5558,8 @@ static int ether_parse_dt(struct ether_priv_data *pdata)
int ret = -EINVAL; int ret = -EINVAL;
unsigned int i, mtlq, chan, bitmap; unsigned int i, mtlq, chan, bitmap;
unsigned int dt_pad_calibration_enable; unsigned int dt_pad_calibration_enable;
unsigned int dt_pad_auto_cal_pu_offset;
unsigned int dt_pad_auto_cal_pd_offset;
/* This variable is for DT entry which should not fail bootup */ /* This variable is for DT entry which should not fail bootup */
int ret_val = 0; int ret_val = 0;
@@ -6004,6 +6006,44 @@ static int ether_parse_dt(struct ether_priv_data *pdata)
osi_core->padctrl.pad_calibration_enable = dt_pad_calibration_enable; osi_core->padctrl.pad_calibration_enable = dt_pad_calibration_enable;
} }
/* Read pad calibration config reg offset, default 0 */
ret = of_property_read_u32(np, "nvidia,pad_auto_cal_pu_offset",
&dt_pad_auto_cal_pu_offset);
if (ret < 0) {
dev_info(dev, "missing nvidia,pad_auto_cal_pu_offset, "
"setting default 0\n");
osi_core->padctrl.pad_auto_cal_pu_offset = 0U;
ret = 0;
} else if (dt_pad_auto_cal_pu_offset >
OSI_PAD_CAL_CONFIG_PD_PU_OFFSET_MAX) {
dev_err(dev, "Error: Invalid dt "
"pad_auto_cal_pu_offset: %u value\n",
dt_pad_auto_cal_pu_offset);
ret = -EINVAL;
goto exit;
} else {
osi_core->padctrl.pad_auto_cal_pu_offset =
dt_pad_auto_cal_pu_offset;
}
ret = of_property_read_u32(np, "nvidia,pad_auto_cal_pd_offset",
&dt_pad_auto_cal_pd_offset);
if (ret < 0) {
dev_info(dev, "missing nvidia,pad_auto_cal_pd_offset, "
"setting default 0\n");
osi_core->padctrl.pad_auto_cal_pd_offset = 0U;
ret = 0;
} else if (dt_pad_auto_cal_pd_offset >
OSI_PAD_CAL_CONFIG_PD_PU_OFFSET_MAX) {
dev_err(dev, "Error: Invalid dt "
"pad_auto_cal_pu_offset: %u value\n",
dt_pad_auto_cal_pd_offset);
ret = -EINVAL;
goto exit;
} else {
osi_core->padctrl.pad_auto_cal_pd_offset =
dt_pad_auto_cal_pd_offset;
}
pdata->pin = devm_pinctrl_get(dev); pdata->pin = devm_pinctrl_get(dev);
if (IS_ERR(pdata->pin)) { if (IS_ERR(pdata->pin)) {
dev_err(dev, "DT: missing eqos pinctrl device\n"); dev_err(dev, "DT: missing eqos pinctrl device\n");