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platform: tegra: Update DRAM clk to MC clk formula
As per info received from HW team, we should not hardcode 1600 in DRAM clock to MC clock conversion function. DRAM clk to EMC clk ratio is always 4:1 while EMC clk to MC clk ratio can be found in CAR register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0.MC_EMC_SAME_FREQ bit. If it's 0 then MC frequency is half of EMC frequency, otherwise MC freq is same as EMC freq. Hence update DRAM clock to MC clock function as per above logic. Bug 4090660 Change-Id: I5a7586aeee29fe1c98437cf0dd5b820d8f540072 Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2915138 Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -161,6 +161,32 @@ static unsigned long dram_clk_to_mc_clk_t23x(unsigned long dram_clk)
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return mc_clk;
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}
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static unsigned long dram_clk_to_mc_clk_t26x(unsigned long dram_clk)
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{
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u64 top_car_base_reg = 0x8102000000;
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u64 top_car_size_reg = 0x8103ffffff;
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void __iomem *clk_rst_base = NULL;
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u32 clk_rst_clk_source_emcsa_0 = 0x102000;
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u32 mc_emc_freq_same = 4, clk_info = 0;
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unsigned long mc_clk;
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clk_rst_base = ioremap(top_car_base_reg, top_car_size_reg);
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if (!clk_rst_base) {
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pr_err("Failed to ioremap clk rst\n");
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return 0;
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}
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clk_info = readl(clk_rst_base + clk_rst_clk_source_emcsa_0);
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mc_emc_freq_same = clk_info >> 16 & 0x1;
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if (mc_emc_freq_same == 1)
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mc_clk = dram_clk / 4;
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else
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mc_clk = dram_clk / 8;
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iounmap(clk_rst_base);
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return mc_clk;
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}
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unsigned long dram_clk_to_mc_clk(unsigned long dram_clk)
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{
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return ops->dram_clk_to_mc_clk(dram_clk);
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@@ -350,7 +376,7 @@ static struct mc_utils_ops mc_utils_t26x_ops = {
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.emc_bw_to_freq = emc_bw_to_freq_t23x,
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.tegra_dram_types = tegra_dram_types_t26x,
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.get_dram_num_channels = get_dram_num_channels_t26X,
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.dram_clk_to_mc_clk = dram_clk_to_mc_clk_t23x,
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.dram_clk_to_mc_clk = dram_clk_to_mc_clk_t26x,
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};
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static int __init tegra_mc_utils_init_t26x(void)
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