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platform: tegra: Update DRAM clk to MC clk formula

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As per info received from HW team, we should not hardcode 1600 in DRAM
clock to MC clock conversion function. DRAM clk to EMC clk ratio is
always 4:1 while EMC clk to MC clk ratio can be found in CAR register
CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0.MC_EMC_SAME_FREQ bit.
If it's 0 then MC frequency is half of EMC frequency, otherwise MC freq
is same as EMC freq. Hence update DRAM clock to MC clock function as per
above logic.

Bug 4090660

Change-Id: I5a7586aeee29fe1c98437cf0dd5b820d8f540072
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2915138
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ketan Patil
2023-06-02 12:43:51 +00:00
committed by Jon Hunter
parent 13412069a0
commit 446ff87f28
1 changed files with 27 additions and 1 deletions
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28
drivers/platform/tegra/mc-utils/mc-utils.c
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@@ -161,6 +161,32 @@ static unsigned long dram_clk_to_mc_clk_t23x(unsigned long dram_clk)
return mc_clk; return mc_clk;
} }
static unsigned long dram_clk_to_mc_clk_t26x(unsigned long dram_clk)
{
u64 top_car_base_reg = 0x8102000000;
u64 top_car_size_reg = 0x8103ffffff;
void __iomem *clk_rst_base = NULL;
u32 clk_rst_clk_source_emcsa_0 = 0x102000;
u32 mc_emc_freq_same = 4, clk_info = 0;
unsigned long mc_clk;
clk_rst_base = ioremap(top_car_base_reg, top_car_size_reg);
if (!clk_rst_base) {
pr_err("Failed to ioremap clk rst\n");
return 0;
}
clk_info = readl(clk_rst_base + clk_rst_clk_source_emcsa_0);
mc_emc_freq_same = clk_info >> 16 & 0x1;
if (mc_emc_freq_same == 1)
mc_clk = dram_clk / 4;
else
mc_clk = dram_clk / 8;
iounmap(clk_rst_base);
return mc_clk;
}
unsigned long dram_clk_to_mc_clk(unsigned long dram_clk) unsigned long dram_clk_to_mc_clk(unsigned long dram_clk)
{ {
return ops->dram_clk_to_mc_clk(dram_clk); return ops->dram_clk_to_mc_clk(dram_clk);
@@ -350,7 +376,7 @@ static struct mc_utils_ops mc_utils_t26x_ops = {
.emc_bw_to_freq = emc_bw_to_freq_t23x, .emc_bw_to_freq = emc_bw_to_freq_t23x,
.tegra_dram_types = tegra_dram_types_t26x, .tegra_dram_types = tegra_dram_types_t26x,
.get_dram_num_channels = get_dram_num_channels_t26X, .get_dram_num_channels = get_dram_num_channels_t26X,
.dram_clk_to_mc_clk = dram_clk_to_mc_clk_t23x, .dram_clk_to_mc_clk = dram_clk_to_mc_clk_t26x,
}; };
static int __init tegra_mc_utils_init_t26x(void) static int __init tegra_mc_utils_init_t26x(void)