ASoC: tegra-alt: Use flat regcache

When using RBTREE cache, there can be allocations the first time
a register is accessed. This can cause an attempt to schedule while
atomic in the case that the regmap is using a spinlock. This can be
resolved by using a flat cache.

Bug 200041820

Change-Id: Id69592cd5fadbb5ad9ccfdbb1f184733a332512c
Signed-off-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Reviewed-on: http://git-master/r/552940
This commit is contained in:
Arun Shamanna Lakshmi
2014-10-02 10:24:44 -07:00
committed by Sameer Pujar
parent 684a5ee845
commit 5066fe1a3a
15 changed files with 15 additions and 15 deletions

View File

@@ -110,7 +110,7 @@ static const struct regmap_config tegra210_admaif_regmap_config = {
.writeable_reg = tegra210_admaif_wr_reg, .writeable_reg = tegra210_admaif_wr_reg,
.readable_reg = tegra210_admaif_rd_reg, .readable_reg = tegra210_admaif_rd_reg,
.volatile_reg = tegra210_admaif_volatile_reg, .volatile_reg = tegra210_admaif_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static void tegra210_admaif_global_enable(struct tegra210_admaif *admaif, static void tegra210_admaif_global_enable(struct tegra210_admaif *admaif,

View File

@@ -592,7 +592,7 @@ static const struct regmap_config tegra210_adx_regmap_config = {
.writeable_reg = tegra210_adx_wr_reg, .writeable_reg = tegra210_adx_wr_reg,
.readable_reg = tegra210_adx_rd_reg, .readable_reg = tegra210_adx_rd_reg,
.volatile_reg = tegra210_adx_volatile_reg, .volatile_reg = tegra210_adx_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_adx_soc_data soc_data_tegra210 = { static const struct tegra210_adx_soc_data soc_data_tegra210 = {

View File

@@ -325,7 +325,7 @@ static const struct regmap_config tegra210_afc_regmap_config = {
.writeable_reg = tegra210_afc_wr_rd_reg, .writeable_reg = tegra210_afc_wr_rd_reg,
.readable_reg = tegra210_afc_wr_rd_reg, .readable_reg = tegra210_afc_wr_rd_reg,
.volatile_reg = tegra210_afc_volatile_reg, .volatile_reg = tegra210_afc_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_afc_soc_data soc_data_tegra210 = { static const struct tegra210_afc_soc_data soc_data_tegra210 = {

View File

@@ -625,7 +625,7 @@ static const struct regmap_config tegra210_amx_regmap_config = {
.writeable_reg = tegra210_amx_wr_reg, .writeable_reg = tegra210_amx_wr_reg,
.readable_reg = tegra210_amx_rd_reg, .readable_reg = tegra210_amx_rd_reg,
.volatile_reg = tegra210_amx_volatile_reg, .volatile_reg = tegra210_amx_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_amx_soc_data soc_data_tegra210 = { static const struct tegra210_amx_soc_data soc_data_tegra210 = {

View File

@@ -270,7 +270,7 @@ static const struct regmap_config tegra210_dmic_regmap_config = {
.readable_reg = tegra210_dmic_rd_reg, .readable_reg = tegra210_dmic_rd_reg,
.volatile_reg = tegra210_dmic_volatile_reg, .volatile_reg = tegra210_dmic_volatile_reg,
.precious_reg = NULL, .precious_reg = NULL,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_dmic_soc_data soc_data_tegra210 = { static const struct tegra210_dmic_soc_data soc_data_tegra210 = {

View File

@@ -721,7 +721,7 @@ static const struct regmap_config tegra210_i2s_regmap_config = {
.writeable_reg = tegra210_i2s_wr_reg, .writeable_reg = tegra210_i2s_wr_reg,
.readable_reg = tegra210_i2s_rd_reg, .readable_reg = tegra210_i2s_rd_reg,
.volatile_reg = tegra210_i2s_volatile_reg, .volatile_reg = tegra210_i2s_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_i2s_soc_data soc_data_tegra210 = { static const struct tegra210_i2s_soc_data soc_data_tegra210 = {

View File

@@ -289,7 +289,7 @@ static const struct regmap_config tegra210_iqc_regmap_config = {
.writeable_reg = tegra210_iqc_wr_reg, .writeable_reg = tegra210_iqc_wr_reg,
.readable_reg = tegra210_iqc_rd_reg, .readable_reg = tegra210_iqc_rd_reg,
.volatile_reg = tegra210_iqc_volatile_reg, .volatile_reg = tegra210_iqc_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_iqc_soc_data soc_data_tegra210 = { static const struct tegra210_iqc_soc_data soc_data_tegra210 = {

View File

@@ -579,7 +579,7 @@ static const struct regmap_config tegra210_mbdrc_regmap_config = {
.readable_reg = tegra210_mbdrc_rd_reg, .readable_reg = tegra210_mbdrc_rd_reg,
.volatile_reg = tegra210_mbdrc_volatile_reg, .volatile_reg = tegra210_mbdrc_volatile_reg,
.precious_reg = tegra210_mbdrc_precious_reg, .precious_reg = tegra210_mbdrc_precious_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
int tegra210_mbdrc_codec_init(struct snd_soc_codec *codec) int tegra210_mbdrc_codec_init(struct snd_soc_codec *codec)

View File

@@ -524,7 +524,7 @@ static const struct regmap_config tegra210_mixer_regmap_config = {
.readable_reg = tegra210_mixer_rd_reg, .readable_reg = tegra210_mixer_rd_reg,
.volatile_reg = tegra210_mixer_volatile_reg, .volatile_reg = tegra210_mixer_volatile_reg,
.precious_reg = tegra210_mixer_precious_reg, .precious_reg = tegra210_mixer_precious_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_mixer_soc_data soc_data_tegra210 = { static const struct tegra210_mixer_soc_data soc_data_tegra210 = {

View File

@@ -369,7 +369,7 @@ static const struct regmap_config tegra210_mvc_regmap_config = {
.writeable_reg = tegra210_mvc_wr_rd_reg, .writeable_reg = tegra210_mvc_wr_rd_reg,
.readable_reg = tegra210_mvc_wr_rd_reg, .readable_reg = tegra210_mvc_wr_rd_reg,
.volatile_reg = tegra210_mvc_volatile_reg, .volatile_reg = tegra210_mvc_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_mvc_soc_data soc_data_tegra210 = { static const struct tegra210_mvc_soc_data soc_data_tegra210 = {

View File

@@ -283,7 +283,7 @@ static const struct regmap_config tegra210_ope_regmap_config = {
.writeable_reg = tegra210_ope_wr_reg, .writeable_reg = tegra210_ope_wr_reg,
.readable_reg = tegra210_ope_rd_reg, .readable_reg = tegra210_ope_rd_reg,
.volatile_reg = tegra210_ope_volatile_reg, .volatile_reg = tegra210_ope_volatile_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_ope_soc_data soc_data_tegra210 = { static const struct tegra210_ope_soc_data soc_data_tegra210 = {

View File

@@ -225,7 +225,7 @@ static const struct regmap_config tegra210_peq_regmap_config = {
.readable_reg = tegra210_peq_rd_reg, .readable_reg = tegra210_peq_rd_reg,
.volatile_reg = tegra210_peq_volatile_reg, .volatile_reg = tegra210_peq_volatile_reg,
.precious_reg = tegra210_peq_precious_reg, .precious_reg = tegra210_peq_precious_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
int tegra210_peq_codec_init(struct snd_soc_codec *codec) int tegra210_peq_codec_init(struct snd_soc_codec *codec)

View File

@@ -427,7 +427,7 @@ static const struct regmap_config tegra210_sfc_regmap_config = {
.readable_reg = tegra210_sfc_rd_reg, .readable_reg = tegra210_sfc_rd_reg,
.volatile_reg = tegra210_sfc_volatile_reg, .volatile_reg = tegra210_sfc_volatile_reg,
.precious_reg = tegra210_sfc_precious_reg, .precious_reg = tegra210_sfc_precious_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_sfc_soc_data soc_data_tegra210 = { static const struct tegra210_sfc_soc_data soc_data_tegra210 = {

View File

@@ -315,7 +315,7 @@ static const struct regmap_config tegra210_spdif_regmap_config = {
.max_register = TEGRA210_SPDIF_LCOEF_2_4_2, .max_register = TEGRA210_SPDIF_LCOEF_2_4_2,
.writeable_reg = tegra210_spdif_wr_rd_reg, .writeable_reg = tegra210_spdif_wr_rd_reg,
.readable_reg = tegra210_spdif_wr_rd_reg, .readable_reg = tegra210_spdif_wr_rd_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static const struct tegra210_spdif_soc_data soc_data_tegra210 = { static const struct tegra210_spdif_soc_data soc_data_tegra210 = {

View File

@@ -40,7 +40,7 @@ static const struct regmap_config tegra210_xbar_regmap_config = {
.reg_stride = 4, .reg_stride = 4,
.max_register = TEGRA210_XBAR_PART2_RX + (TEGRA210_XBAR_RX_STRIDE * .max_register = TEGRA210_XBAR_PART2_RX + (TEGRA210_XBAR_RX_STRIDE *
(TEGRA210_XBAR_AUDIO_RX_COUNT - 1)), (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)),
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_FLAT,
}; };
static int tegra210_xbar_runtime_suspend(struct device *dev) static int tegra210_xbar_runtime_suspend(struct device *dev)