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drm/tegra: Add NVDEC support

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Support NVDEC (both instances on Tegra194).

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: I8f6c841a16103fbf37bff3a3440d69059f2644f0
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2532426
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mikko Perttunen
2021-04-13 14:47:28 +03:00
committed by Laxman Dewangan
parent 7171a758d3
commit 558557ab02
2 changed files with 20 additions and 0 deletions
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18
drivers/gpu/host1x/dev.c
View File

@@ -132,6 +132,12 @@ static const struct host1x_sid_entry tegra186_sid_table[] = {
.offset = 0x30, .offset = 0x30,
.limit = 0x34 .limit = 0x34
}, },
{
/* NVDEC */
.base = 0x1b00,
.offset = 0x30,
.limit = 0x34
},
}; };
static const struct host1x_info host1x06_info = { static const struct host1x_info host1x06_info = {
@@ -156,6 +162,18 @@ static const struct host1x_sid_entry tegra194_sid_table[] = {
.offset = 0x30, .offset = 0x30,
.limit = 0x34 .limit = 0x34
}, },
{
/* NVDEC */
.base = 0x1b00,
.offset = 0x30,
.limit = 0x34
},
{
/* NVDEC1 */
.base = 0x1bc0,
.offset = 0x30,
.limit = 0x34
},
}; };
static const struct host1x_info host1x07_info = { static const struct host1x_info host1x07_info = {

2
drivers/gpu/host1x/include/linux/host1x-next.h
View File

@@ -15,6 +15,8 @@ enum host1x_class {
HOST1X_CLASS_GR2D_SB = 0x52, HOST1X_CLASS_GR2D_SB = 0x52,
HOST1X_CLASS_VIC = 0x5D, HOST1X_CLASS_VIC = 0x5D,
HOST1X_CLASS_GR3D = 0x60, HOST1X_CLASS_GR3D = 0x60,
HOST1X_CLASS_NVDEC = 0xF0,
HOST1X_CLASS_NVDEC1 = 0xF5,
}; };
struct host1x; struct host1x;