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t264: Changes to support SMMU on OESP

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1. No need to handle OESP case separately to load
values into mailbox registers.
2. OESP now supports SMMU one can use DRAM to share data.

Bug 3247553

Signed-off-by: rajangam <rajangam@nvidia.com>

Change-Id: I0463d1ccf26f173a1bea9304373cbad192e58d20
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3211209
Tested-by: Jason Li (SW-TEGRA) <jasl@nvidia.com>
Reviewed-by: David Pu <dpu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Jason Li (SW-TEGRA) <jasl@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rajangam
2024-09-10 23:09:06 +00:00
committed by Jon Hunter
parent 1440655254
commit 6163a70525
1 changed files with 7 additions and 15 deletions
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22
drivers/platform/tegra/psc/psc_debug.c
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@@ -364,21 +364,13 @@ static long xfer_data(struct file *file, char __user *data)
dev_dbg(dev, "tx_virt:%p, tx_phys: %p\n", tx_virt, (void *)tx_phys);
dev_dbg(dev, "rx_virt:%p, rx_phys: %p\n", rx_virt, (void *)rx_phys);
/* For OESP/SB */
if (strcmp(psc_name, "oesp") == 0 || strcmp(psc_name, "sb") == 0) {
msg.data[0] = info.opcode[0];
msg.data[1] = info.opcode[1];
if (info.tx_buf && info.tx_size > 0 && info.tx_size <= 56)
memcpy(&msg.data[2], tx_virt, info.tx_size);
} else if (strcmp(psc_name, "psc") == 0) {
/* For PSC */
msg.opcode[0] = info.opcode[0];
msg.opcode[1] = info.opcode[1];
msg.tx_iova = tx_phys;
msg.rx_iova = rx_phys;
msg.tx_size = info.tx_size;
msg.rx_size = info.rx_size;
}
/* For all PSC Instances */
msg.opcode[0] = info.opcode[0];
msg.opcode[1] = info.opcode[1];
msg.tx_iova = tx_phys;
msg.rx_iova = rx_phys;
msg.tx_size = info.tx_size;
msg.rx_size = info.rx_size;
ret = send_msg_block(dbg, &msg);
if (ret != 0)