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memory: tegra: Restrict access to non-PERMUX registers

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SOC-HWPM shouldn't request read/write to non-PERMUX registers of
MC-Channels or MSS-HUB. If it does, restrict the access and return
error.

Bug 4704678

Change-Id: I03bae82dfcf4bb9b63e135132b03b5b1e67632f1
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3198241
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Ketan Patil <ketanp@nvidia.com>
This commit is contained in:
Ashish Mhetre
2024-08-22 06:02:51 +00:00
committed by Jon Hunter
parent ba80679071
commit 6d78ed22c7
1 changed files with 11 additions and 1 deletions
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12
drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c
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@@ -15,6 +15,10 @@
#include <uapi/linux/tegra-soc-hwpm-uapi.h>
#define MC_MCC_CTL_PERFMUX_OFFSET 0x8914
#define MC_MCC_DP_PERFMUX_OFFSET 0x8918
#define MC_CBRIDGE_PERFMUX_OFFSET 0x891c
#define MAX_MC_CHANNELS 17 // Broadcast Channel + 16 MC Channels
static struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
@@ -57,10 +61,16 @@ static int tegra_mc_hwpm_reg_op(void *ip_dev,
}
if (inst_element_index >= mc->no_ch) {
pr_err("Incorrect channel number: %u\n", inst_element_index);
dev_err(dev, "Incorrect channel number: %u\n", inst_element_index);
return -EINVAL;
}
if (reg_offset != MC_MCC_CTL_PERFMUX_OFFSET && reg_offset != MC_MCC_DP_PERFMUX_OFFSET &&
reg_offset != MC_CBRIDGE_PERFMUX_OFFSET) {
dev_err(dev, "SOC-HWPM requesting access to prohibited register");
return -EPERM;
}
if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_READ) {
*reg_data = mc_readl(mc, inst_element_index, (u32)reg_offset);
} else if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_WRITE) {