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t234: Move tegra234 DTS/DTSI files to hardware/nvidia

Browse Source 
Move DTS and DTSI files of Tegra234 to the /hardware/nvidia
respective folders part of DTS/DTSI re-organisation and
independent of nvidia-oot.

Following are movement:
      hardware/nvidia/soc/generic-dts/t23x
		tegra234-soc-base.dtsi
		tegra234-soc-display-overlay.dtsi
		tegra234-soc-overlay.dtsi
		tegra234-audio-dai-links-overlay.dtsi

      hardware/nvidia/platform/t23x/concord/dts/generic-dts
		tegra234-carveouts.dts
		tegra234-jetson.dts
		tegra234-dcb-p3737-0000-p3701-0000.dtsi
		tegra234-p3701-0000-overlay.dtsi
		tegra234-p3737-0000+p3701-0000-overlay.dts
		tegra234-p3737-0000-overlay.dtsi
		tegra234-sbsa-uart.dts
      hardware/nvidia/platform/t23x/firespray/dts/generic-dts
		tegra234-p3710-0010-a01-linux-native.dts
		tegra234-p3710-0010-a04-linux-native.dts
		tegra234-p3710-0020-a01-linux-native.dts

Bug 3523182

Change-Id: Ibdecf2fee4a392d9f462405eb229f0984b82ad07
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2808093
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Laxman Dewangan
2022-11-13 06:39:57 +00:00
committed by mobile promotions
parent e1f7bf59ed
commit 7f81325068
15 changed files with 0 additions and 6342 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm64/boot/dts/nvidia/Makefile
View File

@@ -4,17 +4,5 @@
# DT overlays
dtbo-y += tegra-optee.dtbo
dtbo-y += tegra194-carveouts.dtbo
dtbo-y += tegra234-carveouts.dtbo
dtbo-y += tegra194-jetson.dtbo
dtbo-y += tegra194-p3509-0000+p3668-0001-overlay.dtbo
dtbo-y += tegra234-p3737-0000+p3701-0000-overlay.dtbo
dtbo-y += tegra234-jetson.dtbo
dtbo-y += tegra234-sbsa-uart.dtbo
# Nvidia internal DT platforms
# firespray DT
dtb-y += tegra234-p3710-0010-a01-linux-native.dtb
dtb-y += tegra234-p3710-0010-a04-linux-native.dtb
dtb-y += tegra234-p3710-0020-a01-linux-native.dtb

2285
arch/arm64/boot/dts/nvidia/tegra234-audio-dai-links-overlay.dtsi
View File

File diff suppressed because it is too large Load Diff

38
arch/arm64/boot/dts/nvidia/tegra234-carveouts.dts
View File

@@ -1,38 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = "/";
__overlay__ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
vpr: vpr-carveout {
compatible = "nvidia,vpr-carveout";
status = "okay";
};
fsi_reserved: fsi-carveout {
compatible = "nvidia,fsi-carveout";
size = <0 0x2000000>;
alignment = <0 0x1000>;
no-map;
alloc-ranges = <0x0 0x0 0x1 0x0>;
status = "okay";
};
};
tegra-carveouts {
compatible = "nvidia,carveouts";
memory-region = <&vpr &fsi_reserved>;
status = "okay";
};
};
};
};

551
arch/arm64/boot/dts/nvidia/tegra234-dcb-p3737-0000-p3701-0000.dtsi
View File

@@ -1,551 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/ {
fragment-t234-dcb@0 {
target-path = "/";
__overlay__ {
display@13800000 {
nvidia,dcb-image = [
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80 fe ff ff ff 00 00 00 00 71 71 98 07 01 00 00
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1d 00 00 2f 1e 00 00 b7 1e 00 00 3f 1f 00 00 c7
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08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
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00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 ];
};
};
};
};

389
arch/arm64/boot/dts/nvidia/tegra234-jetson.dts
View File

@@ -1,389 +0,0 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES.
*
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
#define TEGRA234_CLK_NVJPG1 20U
#define TEGRA234_CLK_GPC0CLK 41U
#define TEGRA234_CLK_NVDEC 83U
#define TEGRA234_CLK_NVENC 89U
#define TEGRA234_CLK_NVJPG 90U
#define TEGRA234_CLK_TSEC_PKA 154U
#define TEGRA234_CLK_DLA0_FALCON 174U
#define TEGRA234_CLK_DLA0_CORE 175U
#define TEGRA234_CLK_DLA1_FALCON 176U
#define TEGRA234_CLK_DLA1_CORE 177U
#define TEGRA234_CLK_NAFLL_PVA0_CORE 211U
#define TEGRA234_CLK_NAFLL_PVA0_VPS 212U
#define TEGRA234_CLK_GPC1CLK 236U
#define TEGRA234_CLK_PVA0_CPU_AXI 295U
#define TEGRA234_CLK_PVA0_VPS 297U
#define TEGRA234_CLK_GPUSYS 304U
#define TEGRA234_CLK_OFA 334U
#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c
#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b
#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c
#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d
#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e
#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f
#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a
#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d
#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e
#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e
#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f
#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78
#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79
#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e
#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f
#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe
#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf
#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0
#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1
#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2
#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3
#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4
#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5
#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6
#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7
#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8
#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9
#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca
#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb
#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9
#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea
#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb
#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec
#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0
#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123
#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124
#define TEGRA234_RESET_DLA0 6U
#define TEGRA234_RESET_DLA1 7U
#define TEGRA234_RESET_OFA 9U
#define TEGRA234_RESET_NVJPG1 10U
#define TEGRA234_RESET_GPU 19U
#define TEGRA234_RESET_NVDEC 44U
#define TEGRA234_RESET_NVENC 59U
#define TEGRA234_RESET_NVJPG 61U
#define TEGRA234_RESET_PVA0_ALL 66U
#define TEGRA234_POWER_DOMAIN_OFA 1U
#define TEGRA234_POWER_DOMAIN_NVDEC 23U
#define TEGRA234_POWER_DOMAIN_NVJPGA 24U
#define TEGRA234_POWER_DOMAIN_NVENC 25U
#define TEGRA234_POWER_DOMAIN_VIC 29U
#define TEGRA234_POWER_DOMAIN_PVA 30U
#define TEGRA234_POWER_DOMAIN_DLAA 32U
#define TEGRA234_POWER_DOMAIN_DLAB 33U
#define TEGRA234_POWER_DOMAIN_GPU 35U
#define TEGRA234_POWER_DOMAIN_NVJPGB 36U
#define TEGRA234_SID_NVDLA1 0x23
#define TEGRA234_SID_NVENC 0x24
#define TEGRA234_SID_NVJPG1 0x25
#define TEGRA234_SID_OFA 0x26
#define TEGRA234_SID_PVA0_VM0 0x12U
#define TEGRA234_SID_PVA0_VM1 0x13U
#define TEGRA234_SID_PVA0_VM2 0x14U
#define TEGRA234_SID_PVA0_VM3 0x15U
#define TEGRA234_SID_PVA0_VM4 0x16U
#define TEGRA234_SID_PVA0_VM5 0x17U
#define TEGRA234_SID_PVA0_VM6 0x18U
#define TEGRA234_SID_PVA0_VM7 0x19U
#define TEGRA234_SID_NVDEC 0x29
#define TEGRA234_SID_NVJPG 0x2a
#define TEGRA234_SID_NVDLA0 0x2B
#define TEGRA234_SID_PVA0 0x2C
/ {
overlay-name = "Tegra234 Jetson Overlay";
compatible = "nvidia,tegra234";
fragment@0 {
target-path = "/bus@0/host1x@13e00000";
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0x14800000 0x14800000 0x02000000>,
<0x24700000 0x24700000 0x00080000>;
nvjpg@15380000 {
compatible = "nvidia,tegra234-nvjpg";
reg = <0x15380000 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA234_RESET_NVJPG>;
reset-names = "nvjpg";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGA>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPGSRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVJPGSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso1 TEGRA234_SID_NVJPG>;
dma-coherent;
nvidia,host1x-class = <0xc0>;
};
nvdec@15480000 {
compatible = "nvidia,tegra234-nvdec";
reg = <0x15480000 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVDEC>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_TSEC_PKA>;
clock-names = "nvdec", "fuse", "tsec_pka";
resets = <&bpmp TEGRA234_RESET_NVDEC>;
reset-names = "nvdec";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
dma-coherent;
nvidia,memory-controller = <&mc>;
};
nvenc@154c0000 {
compatible = "nvidia,tegra234-nvenc";
reg = <0x154c0000 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA234_RESET_NVENC>;
reset-names = "nvenc";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVENC>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVENCSRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVENCSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_NVENC>;
dma-coherent;
};
nvjpg@15540000 {
compatible = "nvidia,tegra234-nvjpg";
reg = <0x15540000 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVJPG1>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA234_RESET_NVJPG1>;
reset-names = "nvjpg";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGB>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPG1SRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVJPG1SWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_NVJPG1>;
dma-coherent;
nvidia,host1x-class = <0x07>;
};
nvdla0: nvdla0@15880000 {
compatible = "nvidia,tegra234-nvdla";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>;
reg = <0x15880000 0x00040000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
resets = <&bpmp TEGRA234_RESET_DLA0>;
clocks = <&bpmp TEGRA234_CLK_DLA0_CORE>,
<&bpmp TEGRA234_CLK_DLA0_FALCON>;
clock-names = "nvdla0", "nvdla0_flcn";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA0RDA &emc>,
<&mc TEGRA234_MEMORY_CLIENT_DLA0FALRDB &emc>,
<&mc TEGRA234_MEMORY_CLIENT_DLA0WRA &emc>,
<&mc TEGRA234_MEMORY_CLIENT_DLA0FALWRB &emc>;
interconnect-names = "dma-mem", "read-1", "write", "write-1";
iommus = <&smmu_niso1 TEGRA234_SID_NVDLA0>;
dma-coherent;
status = "okay";
};
nvdla1: nvdla1@158c0000 {
compatible = "nvidia,tegra234-nvdla";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>;
reg = <0x158c0000 0x00040000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
resets = <&bpmp TEGRA234_RESET_DLA1>;
clocks = <&bpmp TEGRA234_CLK_DLA1_CORE>,
<&bpmp TEGRA234_CLK_DLA1_FALCON>;
clock-names = "nvdla1", "nvdla1_flcn";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA1RDA &emc>,
<&mc TEGRA234_MEMORY_CLIENT_DLA1FALRDB &emc>,
<&mc TEGRA234_MEMORY_CLIENT_DLA1WRA &emc>,
<&mc TEGRA234_MEMORY_CLIENT_DLA1FALWRB &emc>;
interconnect-names = "dma-mem", "read-1", "write", "write-1";
iommus = <&smmu_niso0 TEGRA234_SID_NVDLA1>;
dma-coherent;
status = "okay";
};
ofa@15a50000 {
compatible = "nvidia,tegra234-ofa";
reg = <0x15a50000 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_OFA>;
clock-names = "ofa";
resets = <&bpmp TEGRA234_RESET_OFA>;
reset-names = "ofa";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_OFA>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_OFAR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_OFAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_OFA>;
dma-coherent;
};
pva0: pva0@16000000 {
compatible = "nvidia,tegra234-pva";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>;
reg = <0x16000000 0x800000>,
<0x24700000 0x080000>;
interrupts = <0 234 0x04>,
<0 432 0x04>,
<0 433 0x04>,
<0 434 0x04>,
<0 435 0x04>,
<0 436 0x04>,
<0 437 0x04>,
<0 438 0x04>,
<0 439 0x04>;
resets = <&bpmp TEGRA234_RESET_PVA0_ALL>;
clocks = <&bpmp TEGRA234_CLK_PVA0_CPU_AXI>,
<&bpmp TEGRA234_CLK_NAFLL_PVA0_VPS>,
<&bpmp TEGRA234_CLK_PVA0_VPS>;
clock-names = "axi", "vps0", "vps1";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0>;
dma-coherent;
status = "okay";
pva0_ctx0n1: pva0_niso1_ctx0 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM0>;
dma-coherent;
status = "okay";
};
pva0_ctx1n1: pva0_niso1_ctx1 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM1>;
dma-coherent;
status = "okay";
};
pva0_ctx2n1: pva0_niso1_ctx2 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM2>;
dma-coherent;
status = "okay";
};
pva0_ctx3n1: pva0_niso1_ctx3 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM3>;
dma-coherent;
status = "okay";
};
pva0_ctx4n1: pva0_niso1_ctx4 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM4>;
dma-coherent;
status = "okay";
};
pva0_ctx5n1: pva0_niso1_ctx5 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM5>;
dma-coherent;
status = "okay";
};
pva0_ctx6n1: pva0_niso1_ctx6 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM6>;
dma-coherent;
status = "okay";
};
pva0_ctx7n1: pva0_niso1_ctx7 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM7>;
dma-coherent;
status = "okay";
};
};
};
};
fragment@1 {
target-path = "/bus@0";
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
gpu@17000000 {
compatible = "nvidia,ga10b";
reg = <0x17000000 0x01000000>,
<0x18000000 0x01000000>,
<0x03b41000 0x00001000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall0", "stall1", "stall2", "nonstall";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
<&bpmp TEGRA234_CLK_GPC0CLK>,
<&bpmp TEGRA234_CLK_GPC1CLK>;
clock-names = "sysclk", "gpc0clk", "gpc1clk";
resets = <&bpmp TEGRA234_RESET_GPU>;
dma-coherent;
nvidia,bpmp = <&bpmp>;
status = "okay";
};
};
};
fragment@2 {
target-path = "/";
__overlay__ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma { /* Needed for nvgpu comptags */
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x10000000>; /* 256MB */
alignment = <0x0 0x10000>;
linux,cma-default;
status = "okay";
};
};
};
};
};

7
arch/arm64/boot/dts/nvidia/tegra234-p3701-0000-overlay.dtsi
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@@ -1,7 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ {
};

87
arch/arm64/boot/dts/nvidia/tegra234-p3710-0010-a01-linux-native.dts
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@@ -1,87 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
#include "tegra234-soc-base.dtsi"
/ {
compatible = "nvidia,tegra234";
bus@0 {
spi@3270000 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <102000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
mmc@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
};
rtc@c2a0000 {
status = "okay";
};
pmc@c360000 {
nvidia,invert-interrupt;
};
};
};
/ {
model = "p3710-0010";
compatible = "nvidia,tegra234";
aliases {
mmc0 = "/bus@0/mmc@3460000";
serial0 = &tcu;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
status = "okay";
force-recovery {
label = "Force Recovery";
gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <BTN_1>;
};
power-key {
label = "Power";
gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_POWER>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
suspend {
label = "Suspend";
gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_SLEEP>;
};
};
serial {
status = "okay";
};
};

87
arch/arm64/boot/dts/nvidia/tegra234-p3710-0010-a04-linux-native.dts
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@@ -1,87 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
#include "tegra234-soc-base.dtsi"
/ {
compatible = "nvidia,tegra234";
bus@0 {
spi@3270000 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <102000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
mmc@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
};
rtc@c2a0000 {
status = "okay";
};
pmc@c360000 {
nvidia,invert-interrupt;
};
};
};
/ {
model = "p3710-0010";
compatible = "nvidia,tegra234";
aliases {
mmc0 = "/bus@0/mmc@3460000";
serial0 = &tcu;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
status = "okay";
force-recovery {
label = "Force Recovery";
gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <BTN_1>;
};
power-key {
label = "Power";
gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_POWER>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
suspend {
label = "Suspend";
gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_SLEEP>;
};
};
serial {
status = "okay";
};
};

87
arch/arm64/boot/dts/nvidia/tegra234-p3710-0020-a01-linux-native.dts
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@@ -1,87 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
#include "tegra234-soc-base.dtsi"
/ {
compatible = "nvidia,tegra234";
bus@0 {
spi@3270000 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <102000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
mmc@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
};
rtc@c2a0000 {
status = "okay";
};
pmc@c360000 {
nvidia,invert-interrupt;
};
};
};
/ {
model = "p3710-0010";
compatible = "nvidia,tegra234";
aliases {
mmc0 = "/bus@0/mmc@3460000";
serial0 = &tcu;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
status = "okay";
force-recovery {
label = "Force Recovery";
gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <BTN_1>;
};
power-key {
label = "Power";
gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_POWER>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
suspend {
label = "Suspend";
gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_SLEEP>;
};
};
serial {
status = "okay";
};
};

275
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000-overlay.dts
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@@ -1,275 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
/plugin/;
#include "tegra234-soc-overlay.dtsi"
#include "tegra234-p3737-0000-overlay.dtsi"
#include "tegra234-p3701-0000-overlay.dtsi"
#include "tegra234-audio-dai-links-overlay.dtsi"
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ {
fragment-t234-p3737-p3701@0 {
target-path = "/bpmp/i2c";
__overlay__ {
vrs@3c {
compatible = "nvidia,vrs-pseq";
reg = <0x3c>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
status = "okay";
vrs_rtc: rtc {
status = "okay";
};
};
};
};
fragment-t234-p3737-p3701@1 {
target-path = "/bus@0/i2c@3160000";
__overlay__ {
status = "okay";
};
};
fragment-t234-p3737-p3701@2 {
target-path = "/bus@0/i2c@c240000";
__overlay__ {
status = "okay";
};
};
fragment-t234-p3737-p3701@3 {
target-path = "/bus@0/i2c@3180000";
__overlay__ {
status = "okay";
};
};
fragment-t234-p3737-p3701@4 {
target-path = "/bus@0/i2c@3190000";
__overlay__ {
status = "okay";
};
};
fragment-t234-p3737-p3701@5 {
target-path = "/bus@0/i2c@31b0000";
__overlay__ {
nvidia,hw-instance-id = <0x5>;
status = "okay";
};
};
fragment-t234-p3737-p3701@6 {
target-path = "/bus@0/i2c@31c0000";
__overlay__ {
status = "okay";
};
};
fragment-t234-p3737-p3701@7 {
target-path = "/bus@0/i2c@c250000";
__overlay__ {
status = "okay";
};
};
fragment-t234-p3737-p3701@8 {
target-path = "/bus@0/i2c@31e0000";
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
rt5640: rt5640.8-001c@1c {
compatible = "realtek,rt5640";
reg = <0x1c>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,dmic1-data-pin = <0>; /* RT5659_DMIC1_NULL */
realtek,dmic2-data-pin = <0>; /* RT5659_DMIC2_NULL */
realtek,jack-detect-source = <7>;
#sound-dai-cells = <1>;
sound-name-prefix = "CVB-RT";
status = "okay";
};
};
};
fragment-t234-p3737-p3701@9 {
target-path = "/";
__overlay__ {
sound {
compatible = "nvidia,tegra186-ape";
clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "pll_a", "pll_a_out0", "extern1";
assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
nvidia-audio-card,name = "NVIDIA Jetson AGX Orin APE";
nvidia-audio-card,widgets =
"Headphone", "CVB-RT Headphone Jack",
"Microphone", "CVB-RT Mic Jack",
"Speaker", "CVB-RT Int Spk",
"Microphone", "CVB-RT Int Mic";
nvidia-audio-card,routing =
"CVB-RT Headphone Jack", "CVB-RT HPOL",
"CVB-RT Headphone Jack", "CVB-RT HPOR",
"CVB-RT IN1P", "CVB-RT Mic Jack",
"CVB-RT IN2P", "CVB-RT Mic Jack",
"CVB-RT Int Spk", "CVB-RT SPOLP",
"CVB-RT Int Spk", "CVB-RT SPORP",
"CVB-RT DMIC1", "CVB-RT Int Mic",
"CVB-RT DMIC2", "CVB-RT Int Mic";
nvidia-audio-card,mclk-fs = <256>;
nvidia-audio-card,dai-link@76 {
link-name = "rt5640-playback";
codec {
sound-dai = <&rt5640 0>;
prefix = "CVB-RT";
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma { /* Needed for nvgpu comptags */
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x10000000>; /* 256MB */
alignment = <0x0 0x10000>;
linux,cma-default;
status = "okay";
};
};
};
};
fragment-t234-p3737-p3701@10 {
target-path = "/cpus";
__overlay__ {
cpu_core_power_states {
C1: c1 {
compatible = "arm,idle-state";
state-name = "Clock gated";
wakeup-latency-us = <1>;
min-residency-us = <1>;
status = "okay";
};
C7: c7 {
compatible = "arm,idle-state";
state-name = "Core powergate";
wakeup-latency-us = <5000>;
arm,psci-suspend-param= <0x40000007>;
min-residency-us = <30000>;
status = "okay";
};
};
};
};
fragment-t234-p3737-p3701@11 {
target-path = "/cpus/cpu@0";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@12 {
target-path = "/cpus/cpu@100";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@13 {
target-path = "/cpus/cpu@200";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@14 {
target-path = "/cpus/cpu@300";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@15 {
target-path = "/cpus/cpu@10000";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@16 {
target-path = "/cpus/cpu@10100";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@17 {
target-path = "/cpus/cpu@10200";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@18 {
target-path = "/cpus/cpu@10300";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@19 {
target-path = "/cpus/cpu@20000";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@20 {
target-path = "/cpus/cpu@20100";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@21 {
target-path = "/cpus/cpu@20200";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
fragment-t234-p3737-p3701@22 {
target-path = "/cpus/cpu@20300";
__overlay__ {
cpu-idle-states = <&C7>;
};
};
};

13
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000-overlay.dtsi
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@@ -1,13 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ {
fragment-t234@0 {
__overlay__ {
ufshci@2500000 {
status = "okay";
};
};
};
};

42
arch/arm64/boot/dts/nvidia/tegra234-sbsa-uart.dts
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@@ -1,42 +0,0 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Tegra234 Device-tree overlay for SBSA UART
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
overlay-name = "Tegra234 SBSA UART overlay";
compatible = "nvidia,tegra234";
fragment@0 {
target-path = "/bus@0/";
__overlay__ {
serial@31d0000 {
compatible = "arm,sbsa-uart";
reg = <0x31d0000 0x10000>;
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
status = "okay";
};
};
};
};

1299
arch/arm64/boot/dts/nvidia/tegra234-soc-base.dtsi
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File diff suppressed because it is too large Load Diff

190
arch/arm64/boot/dts/nvidia/tegra234-soc-display-overlay.dtsi
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@@ -1,190 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <dt-bindings/memory/tegra234-smmu-streamid.h>
#include <dt-bindings/soc/tegra234-powergate.h>
#include <dt-bindings/clock/tegra234-clock-oot.h>
#include <dt-bindings/reset/tegra234-reset-oot.h>
#include <dt-bindings/memory/tegra234-mc-oot.h>
/ {
fragment-t234-display@0 {
target-path = "/";
__overlay__ {
dce@d800000 {
compatible = "nvidia,tegra234-dce";
reg = <0x0 0x0d800000 0x0 0x00800000>;
interrupts =
<0 376 0x4>,
<0 377 0x4>;
interrupt-names = "wdt-remote",
"dce-sm0";
iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
status = "okay";
};
display@13800000 {
compatible = "nvidia,tegra234-display";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
nvidia,num-dpaux-instance = <1>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */
0x0 0x0242c000 0x0 0x1000 /* hdacodec */
0x0 0x03990000 0x0 0x10000>; /* mipical */
interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
interrupts = <0 416 4
0 419 4
0 61 4>;
nvidia,bpmp = <&bpmp>;
clocks = <&bpmp TEGRA234_CLK_HUB>,
<&bpmp TEGRA234_CLK_DISP>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp TEGRA234_CLK_DPAUX>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp TEGRA234_CLK_VPLL0_REF>,
<&bpmp TEGRA234_CLK_VPLL0>,
<&bpmp TEGRA234_CLK_VPLL1>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp TEGRA234_CLK_RG0>,
<&bpmp TEGRA234_CLK_RG1>,
<&bpmp TEGRA234_CLK_DISPPLL>,
<&bpmp TEGRA234_CLK_DISPHUBPLL>,
<&bpmp TEGRA234_CLK_DSI_LP>,
<&bpmp TEGRA234_CLK_DSI_CORE>,
<&bpmp TEGRA234_CLK_DSI_PIXEL>,
<&bpmp TEGRA234_CLK_PRE_SOR0>,
<&bpmp TEGRA234_CLK_PRE_SOR1>,
<&bpmp TEGRA234_CLK_DP_LINK_REF>,
<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp TEGRA234_CLK_RG0_M>,
<&bpmp TEGRA234_CLK_RG1_M>,
<&bpmp TEGRA234_CLK_SOR0_M>,
<&bpmp TEGRA234_CLK_SOR1_M>,
<&bpmp TEGRA234_CLK_PLLHUB>,
<&bpmp TEGRA234_CLK_SOR0>,
<&bpmp TEGRA234_CLK_SOR1>,
<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SF0>,
<&bpmp TEGRA234_CLK_SF0>,
<&bpmp TEGRA234_CLK_SF1>,
<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR0_REF>,
<&bpmp TEGRA234_CLK_SOR1_REF>,
<&bpmp TEGRA234_CLK_OSC>,
<&bpmp TEGRA234_CLK_DSC>,
<&bpmp TEGRA234_CLK_MAUD>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>,
<&bpmp TEGRA234_CLK_AZA_BIT>,
<&bpmp TEGRA234_CLK_MIPI_CAL>,
<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp TEGRA234_CLK_SOR0_DIV>;
clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk",
"nvdisplay_p0_clk",
"nvdisplay_p1_clk",
"dpaux0_clk",
"fuse_clk",
"dsipll_vco_clk",
"dsipll_clkoutpn_clk",
"dsipll_clkouta_clk",
"sppll0_vco_clk",
"sppll0_clkoutpn_clk",
"sppll0_clkouta_clk",
"sppll0_clkoutb_clk",
"sppll0_div10_clk",
"sppll0_div25_clk",
"sppll0_div27_clk",
"sppll1_vco_clk",
"sppll1_clkoutpn_clk",
"sppll1_div27_clk",
"vpll0_ref_clk",
"vpll0_clk",
"vpll1_clk",
"nvdisplay_p0_ref_clk",
"rg0_clk",
"rg1_clk",
"disppll_clk",
"disphubpll_clk",
"dsi_lp_clk",
"dsi_core_clk",
"dsi_pixel_clk",
"pre_sor0_clk",
"pre_sor1_clk",
"dp_link_ref_clk",
"sor_linka_input_clk",
"sor_linka_afifo_clk",
"sor_linka_afifo_m_clk",
"rg0_m_clk",
"rg1_m_clk",
"sor0_m_clk",
"sor1_m_clk",
"pllhub_clk",
"sor0_clk",
"sor1_clk",
"sor_pad_input_clk",
"pre_sf0_clk",
"sf0_clk",
"sf1_clk",
"dsi_pad_input_clk",
"pre_sor0_ref_clk",
"pre_sor1_ref_clk",
"sor0_ref_pll_clk",
"sor1_ref_pll_clk",
"sor0_ref_clk",
"sor1_ref_clk",
"osc_clk",
"dsc_clk",
"maud_clk",
"aza_2xbit_clk",
"aza_bit_clk",
"mipi_cal_clk",
"uart_fst_mipi_cal_clk",
"sor0_div_clk";
resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
<&bpmp TEGRA234_RESET_DPAUX>,
<&bpmp TEGRA234_RESET_DSI_CORE>,
<&bpmp TEGRA234_RESET_MIPI_CAL>;
reset-names = "nvdisplay_reset",
"dpaux0_reset",
"dsi_core_reset",
"mipi_cal_reset";
status = "okay";
nvidia,disp-sw-soc-chip-id = <0x2350>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR>,
<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1>;
interconnect-names = "dma-mem", "read-1";
#endif
iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
dma-coherent;
};
};
};
};
};

980
arch/arm64/boot/dts/nvidia/tegra234-soc-overlay.dtsi
View File

@@ -1,980 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/clock/tegra234-clock-oot.h>
#include <dt-bindings/reset/tegra234-reset.h>
#include <dt-bindings/reset/tegra234-reset-oot.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/memory/tegra234-mc-oot.h>
#include <dt-bindings/memory/tegra234-smmu-streamid.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/tegra234-gpio.h>
#include "tegra234-soc-display-overlay.dtsi"
#define TEGRA234_POWER_DOMAIN_PVA 30U
#define TEGRA234_POWER_DOMAIN_GPU 35U
/ {
overlay-name = "Add nvidia,p3737-0000+p3701-0000 Overlay Support";
compatible = "nvidia,tegra234";
fragment-t234@0 {
target-path = "/bus@0";
__overlay__ {
watchdog@2190000 {
compatible = "nvidia,tegra-wdt-t234";
reg = <0x02190000 0x10000>, /* WDT0 */
<0x02090000 0x10000>, /* TMR0 */
<0x02080000 0x10000>; /* TKE */
interrupts = <7 0x4 8 0x4>; /* TKE shared int */
nvidia,watchdog-index = <0>;
nvidia,timer-index = <7>;
nvidia,enable-on-init;
nvidia,extend-watchdog-suspend;
timeout-sec = <120>;
nvidia,disable-debug-reset;
status = "okay";
};
tegra_pinctrl: pinmux@2430000 {
compatible = "nvidia,tegra234-pinmux";
reg = <0x2430000 0x19100>,
<0xc300000 0x4000>;
#gpio-range-cells = <3>;
status = "okay";
};
tegra_ufs: ufshci@2500000 {
compatible = "tegra234,ufs_variant";
reg = <0x02500000 0x4000>,
<0x02510000 0x1000>,
<0x02518000 0x1000>,
<0x02520000 0x1000>,
<0x02470000 0x4000>,
<0x02480000 0x4000>;
interrupts = < 0 44 0x04 >;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_UFSHCR>,
<&mc TEGRA234_MEMORY_CLIENT_UFSHCW>;
interconnect-names = "dma-mem", "dma-mem";
iommus = <&smmu_niso0 TEGRA234_SID_UFSHC>;
dma-coherent;
clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
<&bpmp TEGRA234_CLK_MPHY_CORE_PLL_FIXED>,
<&bpmp TEGRA234_CLK_MPHY_L0_TX_SYMB>,
<&bpmp TEGRA234_CLK_MPHY_TX_1MHZ_REF>,
<&bpmp TEGRA234_CLK_MPHY_L0_RX_ANA>,
<&bpmp TEGRA234_CLK_MPHY_L0_RX_SYMB>,
<&bpmp TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT>,
<&bpmp TEGRA234_CLK_MPHY_L0_RX_LS_BIT>,
<&bpmp TEGRA234_CLK_MPHY_L1_RX_ANA>,
<&bpmp TEGRA234_CLK_UFSHC>,
<&bpmp TEGRA234_CLK_UFSDEV_REF>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>,
<&bpmp TEGRA234_CLK_CLK_M>,
<&bpmp TEGRA234_CLK_MPHY_FORCE_LS_MODE>,
<&bpmp TEGRA234_CLK_UPHY_PLL3>,
<&bpmp TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV>,
<&bpmp TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV>,
<&bpmp TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV>,
<&bpmp TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV>,
<&bpmp TEGRA234_CLK_MPHY_L0_TX_2X_SYMB>,
<&bpmp TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV>,
<&bpmp TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV>,
<&bpmp TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV>,
<&bpmp TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV>,
<&bpmp TEGRA234_CLK_OSC>;
clock-names = "pllrefe_vcoout", "mphy_core_pll_fixed",
"mphy_l0_tx_symb", "mphy_tx_1mhz_ref",
"mphy_l0_rx_ana", "mphy_l0_rx_symb",
"mphy_l0_tx_ls_3xbit", "mphy_l0_rx_ls_bit",
"mphy_l1_rx_ana", "ufshc", "ufsdev_ref",
"pll_p", "clk_m", "mphy_force_ls_mode",
"uphy_pll3", "mphy_l0_tx_ls_3xbit_div",
"mphy_l0_tx_ls_symb_div",
"mphy_l0_rx_ls_bit_div",
"mphy_l0_rx_ls_symb_div",
"mphy_l0_tx_2x_symb",
"mphy_l0_tx_hs_symb_div",
"mphy_l0_rx_hs_symb_div",
"mphy_l0_tx_mux_symb_div",
"mphy_l0_rx_mux_symb_div", "osc";
resets = <&bpmp TEGRA234_RESET_MPHY_L0_RX>,
<&bpmp TEGRA234_RESET_MPHY_L0_TX>,
<&bpmp TEGRA234_RESET_MPHY_L1_RX>,
<&bpmp TEGRA234_RESET_MPHY_L1_TX>,
<&bpmp TEGRA234_RESET_MPHY_CLK_CTL>,
<&bpmp TEGRA234_RESET_UFSHC>,
<&bpmp TEGRA234_RESET_UFSHC_AXI_M>,
<&bpmp TEGRA234_RESET_UFSHC_LP_SEQ>;
reset-names = "mphy-l0-rx-rst", "mphy-l0-tx-rst",
"mphy-l1-rx-rst", "mphy-l1-tx-rst",
"mphy-clk-ctl-rst", "ufs-rst",
"ufs-axi-m-rst", "ufshc-lp-rst";
nvidia,enable-x2-config;
nvidia,mask-fast-auto-mode;
nvidia,enable-hs-mode;
nvidia,max-hs-gear = <4>;
nvidia,max-pwm-gear = <0>;
vcc-max-microamp = <0>;
vccq-max-microamp = <0>;
vccq2-max-microamp = <0>;
nvidia,configure-uphy-pll3;
status = "disabled";
ufs_variant {
compatible = "tegra234,ufs_variant";
};
};
serial@3110000 {
compatible = "nvidia,tegra194-hsuart";
reg = <0x03110000 0x10000>;
reg-shift = <2>;
interrupts = <0 113 0x04>;
clocks = <&bpmp TEGRA234_CLK_UARTB>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "serial", "parent";
resets = <&bpmp TEGRA234_RESET_UARTB>;
reset-names = "serial";
status = "okay";
};
mmc@3400000 {
compatible = "nvidia,tegra194-sdhci", "nvidia,tegra234-sdhci";
reg = <0x03400000 0x20000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
<&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
<&bpmp TEGRA234_CLK_PLLC4_MUXED>;
assigned-clock-parents =
<&bpmp TEGRA234_CLK_PLLC4_MUXED>,
<&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA234_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout =
<0x07>;
nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <14>;
nvidia,default-trim = <0x8>;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
bus-width = <4>;
cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
disable-wp;
status = "okay";
};
hda@3510000 {
iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
status = "okay";
};
rtc@c2a0000 {
status = "okay";
};
tachometer@39c0000 {
compatible = "nvidia,pwm-tegra234-tachometer";
reg = <0x039c0000 0x10>;
#pwm-cells = <2>;
clocks = <&bpmp TEGRA234_CLK_TACH0>;
clock-names = "tach";
resets = <&bpmp TEGRA234_RESET_TACH0>;
reset-names = "tach";
pulse-per-rev = <2>;
capture-window-length = <2>;
disable-clk-gate;
status = "okay";
};
gpu@17000000 {
compatible = "nvidia,ga10b";
reg = <0x17000000 0x01000000>,
<0x18000000 0x01000000>,
<0x03b41000 0x00001000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall0", "stall1", "stall2", "nonstall";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
<&bpmp TEGRA234_CLK_GPC0CLK>,
<&bpmp TEGRA234_CLK_GPC1CLK>;
clock-names = "sysclk", "gpc0clk", "gpc1clk";
resets = <&bpmp TEGRA234_RESET_GPU>;
dma-coherent;
nvidia,bpmp = <&bpmp>;
status = "okay";
};
smmu_test {
compatible = "nvidia,smmu_test";
iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
status = "okay";
};
aconnect@2900000 {
ahub@2900800 {
compatible = "nvidia,tegra234-ahub-oot";
assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AHUB>;
assigned-parent-clocks = <0>,
<&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clock-rates = <294912000>,
<49152000>,
<81600000>;
#sound-dai-cells = <1>;
/*
* Below modules are upstreamed and present in v5.15,
* but not yet feature complete. Thus use OOT driver
* versions for now.
*/
i2s@2901000 {
compatible = "nvidia,tegra210-i2s-oot";
#sound-dai-cells = <1>;
nvidia,ahub-i2s-id = <0>;
};
i2s@2901100 {
compatible = "nvidia,tegra210-i2s-oot";
#sound-dai-cells = <1>;
nvidia,ahub-i2s-id = <1>;
};
i2s@2901200 {
compatible = "nvidia,tegra210-i2s-oot";
#sound-dai-cells = <1>;
nvidia,ahub-i2s-id = <2>;
status = "okay";
};
i2s@2901300 {
compatible = "nvidia,tegra210-i2s-oot";
#sound-dai-cells = <1>;
nvidia,ahub-i2s-id = <3>;
};
i2s@2901400 {
compatible = "nvidia,tegra210-i2s-oot";
#sound-dai-cells = <1>;
nvidia,ahub-i2s-id = <4>;
status = "okay";
};
i2s@2901500 {
compatible = "nvidia,tegra210-i2s-oot";
#sound-dai-cells = <1>;
nvidia,ahub-i2s-id = <5>;
};
dmic@2904000 {
compatible = "nvidia,tegra210-dmic-oot";
#sound-dai-cells = <1>;
status = "okay";
};
dmic@2904100 {
compatible = "nvidia,tegra210-dmic-oot";
#sound-dai-cells = <1>;
status = "okay";
};
dmic@2904200 {
compatible = "nvidia,tegra210-dmic-oot";
#sound-dai-cells = <1>;
};
dmic@2904300 {
compatible = "nvidia,tegra210-dmic-oot";
#sound-dai-cells = <1>;
status = "okay";
};
dspk@2905000 {
compatible = "nvidia,tegra186-dspk-oot";
#sound-dai-cells = <1>;
status = "okay";
};
dspk@2905100 {
compatible = "nvidia,tegra186-dspk-oot";
#sound-dai-cells = <1>;
status = "okay";
};
admaif@290f000 {
compatible = "nvidia,tegra186-admaif-oot";
#sound-dai-cells = <1>;
};
/*
* Below modules are upstreamed. DT device nodes
* are backported. But drivers are not in v5.15.
* Thus use existing downstream drivers and add
* '#sound-dai-cells' property needed for downstream
* machine driver.
*/
sfc@2902000 {
#sound-dai-cells = <1>;
};
sfc@2902200 {
#sound-dai-cells = <1>;
};
sfc@2902400 {
#sound-dai-cells = <1>;
};
sfc@2902600 {
#sound-dai-cells = <1>;
};
amx@2903000 {
#sound-dai-cells = <1>;
};
amx@2903100 {
#sound-dai-cells = <1>;
};
amx@2903200 {
#sound-dai-cells = <1>;
};
amx@2903300 {
#sound-dai-cells = <1>;
};
adx@2903800 {
#sound-dai-cells = <1>;
};
adx@2903900 {
#sound-dai-cells = <1>;
};
adx@2903a00 {
#sound-dai-cells = <1>;
};
adx@2903b00 {
#sound-dai-cells = <1>;
};
mvc@290a000 {
#sound-dai-cells = <1>;
};
mvc@290a200 {
#sound-dai-cells = <1>;
};
amixer@290bb00 {
#sound-dai-cells = <1>;
};
/* Below modules are upstreamed, but not in v5.15 */
tegra_ope1: processing-engine@2908000 {
compatible = "nvidia,tegra234-ope",
"nvidia,tegra210-ope";
reg = <0x2908000 0x100>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "OPE1";
#sound-dai-cells = <1>;
equalizer@2908100 {
compatible = "nvidia,tegra234-peq",
"nvidia,tegra210-peq";
reg = <0x2908100 0x100>;
};
dynamic-range-compressor@2908200 {
compatible = "nvidia,tegra234-mbdrc",
"nvidia,tegra210-mbdrc";
reg = <0x2908200 0x200>;
};
};
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra194-asrc";
reg = <0x2910000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "ASRC1";
#sound-dai-cells = <1>;
};
/* Below AHUB modules are not yet upstreamed */
tegra_arad: arad@290e400 {
compatible = "nvidia,tegra186-arad";
reg = <0x290e400 0x400>;
#address-cells = <1>;
#size-cells = <1>;
#sound-dai-cells = <1>;
};
tegra_afc1: afc@2907000 {
compatible = "nvidia,tegra234-afc",
"nvidia,tegra186-afc";
reg = <0x2907000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC1";
#sound-dai-cells = <1>;
};
tegra_afc2: afc@2907100 {
compatible = "nvidia,tegra234-afc",
"nvidia,tegra186-afc";
reg = <0x2907100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC2";
#sound-dai-cells = <1>;
};
tegra_afc3: afc@2907200 {
compatible = "nvidia,tegra234-afc",
"nvidia,tegra186-afc";
reg = <0x2907200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC3";
#sound-dai-cells = <1>;
};
tegra_afc4: afc@2907300 {
compatible = "nvidia,tegra234-afc",
"nvidia,tegra186-afc";
reg = <0x2907300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC4";
#sound-dai-cells = <1>;
};
tegra_afc5: afc@2907400 {
compatible = "nvidia,tegra234-afc",
"nvidia,tegra186-afc";
reg = <0x2907400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC5";
#sound-dai-cells = <1>;
};
tegra_afc6: afc@2907500 {
compatible = "nvidia,tegra234-afc",
"nvidia,tegra186-afc";
reg = <0x2907500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC6";
#sound-dai-cells = <1>;
};
};
/*
* Placeholder for ADSP audio device.
* Not required for L4T releases, will be
* enabled as and when needed.
*/
tegra_adsp_audio: adsp_audio {
#sound-dai-cells = <1>;
status = "disabled";
};
};
};
};
fragment-t234@1 {
target-path = "/bus@0/host1x@13e00000";
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0x14800000 0x14800000 0x02000000>,
<0x24700000 0x24700000 0x00080000>;
se@15810000 {
compatible = "nvidia,tegra234-se1-nvhost";
reg = <0x15810000 0x10000>;
supported-algos = "drbg";
nvidia,io-coherent;
opcode_addr = <0x1004>;
clocks = <&bpmp TEGRA234_CLK_SE>;
clock-names = "se";
iommus = <&smmu_niso1 TEGRA234_SID_SES_SE0>;
dma-coherent;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
interconnect-names = "read", "write";
status = "okay";
};
se@15820000 {
compatible = "nvidia,tegra234-se2-nvhost";
reg = <0x15820000 0x10000>;
supported-algos = "aes", "cmac", "xts", "aead";
nvidia,io-coherent;
opcode_addr = <0x2004>;
clocks = <&bpmp TEGRA234_CLK_SE>;
clock-names = "se";
iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>;
dma-coherent;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
interconnect-names = "read", "write";
status = "okay";
};
se@15840000 {
compatible = "nvidia,tegra234-se4-nvhost";
reg = <0x15840000 0x10000>;
supported-algos = "sha", "sha3", "hmac";
nvidia,io-coherent;
opcode_addr = <0x4004>;
clocks = <&bpmp TEGRA234_CLK_SE>;
clock-names = "se";
iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>;
dma-coherent;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
interconnect-names = "read", "write";
status = "okay";
};
tsec@15500000 {
compatible = "nvidia,tegra234-tsec";
reg = <0x15500000 0x00040000>;
interrupts = <0 228 0x04>;
resets = <&bpmp TEGRA234_RESET_TSEC>;
clocks = <&bpmp TEGRA234_CLK_TSEC>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_TSEC_PKA>;
clock-names = "tsec", "efuse", "tsec_pka";
iommus = <&smmu_niso1 TEGRA234_SID_TSEC>;
nvidia,memory-controller = <&mc>;
dma-coherent;
status = "okay";
};
tegra_soc_hwpm {
compatible = "nvidia,t234-soc-hwpm";
dma-coherent;
reg = <0xf100000 0x1000>,
<0xf101000 0x1000>,
<0xf102000 0x1000>,
<0xf103000 0x1000>,
<0xf104000 0x1000>,
<0xf105000 0x1000>,
<0xf106000 0x1000>,
<0xf107000 0x1000>,
<0xf108000 0x1000>,
<0xf109000 0x1000>,
<0xf10a000 0x1000>,
<0xf10b000 0x1000>,
<0xf10c000 0x1000>,
<0xf10d000 0x1000>,
<0xf10e000 0x1000>,
<0xf10f000 0x1000>,
<0xf110000 0x1000>,
<0xf111000 0x1000>,
<0xf112000 0x1000>,
<0xf113000 0x1000>,
<0xf114000 0x1000>,
<0xf115000 0x1000>,
<0xf116000 0x1000>,
<0xf117000 0x1000>,
<0xf118000 0x1000>,
<0xf119000 0x1000>,
<0xf11a000 0x1000>,
<0xf11b000 0x1000>,
<0xf11c000 0x1000>,
<0xf11d000 0x1000>,
<0xf11e000 0x1000>,
<0xf11f000 0x1000>,
<0xf120000 0x1000>,
<0xf121000 0x1000>,
<0xf122000 0x1000>,
<0xf123000 0x1000>,
<0xf124000 0x1000>,
<0xf125000 0x1000>,
<0xf126000 0x1000>,
<0xf127000 0x1000>,
<0xf128000 0x1000>,
<0xf129000 0x1000>,
<0xf12a000 0x1000>,
<0xf12b000 0x1000>,
<0xf12c000 0x1000>,
<0xf12d000 0x1000>,
<0xf12e000 0x1000>,
<0xf12f000 0x1000>,
<0xf130000 0x1000>,
<0xf131000 0x1000>,
<0xf132000 0x1000>,
<0xf133000 0x1000>,
<0xf14a000 0x2000>,
<0xf14d000 0x1000>;
reg-names = "perfmon_vi0",
"perfmon_vi1",
"perfmon_isp0",
"perfmon_vica0",
"perfmon_ofaa0",
"perfmon_pvav0", "perfmon_pvav1", "perfmon_pvac0",
"perfmon_nvdlab0", "perfmon_nvdlab1",
"perfmon_nvdisplay0",
"perfmon_sys0",
"perfmon_mgbe0", "perfmon_mgbe1",
"perfmon_mgbe2", "perfmon_mgbe3",
"perfmon_scf",
"perfmon_nvdeca0",
"perfmon_nvenca0",
"perfmon_mssnvlhsh0",
"perfmon_pcie0", "perfmon_pcie1",
"perfmon_pcie2", "perfmon_pcie3", "perfmon_pcie4",
"perfmon_pcie5", "perfmon_pcie6", "perfmon_pcie7",
"perfmon_pcie8", "perfmon_pcie9", "perfmon_pcie10",
"perfmon_msschannel_parta0",
"perfmon_msschannel_parta1",
"perfmon_msschannel_parta2",
"perfmon_msschannel_parta3",
"perfmon_msschannel_partb0",
"perfmon_msschannel_partb1",
"perfmon_msschannel_partb2",
"perfmon_msschannel_partb3",
"perfmon_msschannel_partc0",
"perfmon_msschannel_partc1",
"perfmon_msschannel_partc2",
"perfmon_msschannel_partc3",
"perfmon_msschannel_partd0",
"perfmon_msschannel_partd1",
"perfmon_msschannel_partd2",
"perfmon_msschannel_partd3",
"perfmon_msshub0", "perfmon_msshub1",
"perfmon_mssmcfclient0", "perfmon_mssmcfmem0",
"perfmon_mssmcfmem1",
"pma", "rtr";
clocks = <&bpmp TEGRA234_CLK_LA>,
<&bpmp TEGRA234_CLK_PLLREFE_VCOOUT_GATED>;
clock-names = "la", "parent";
resets = <&bpmp TEGRA234_RESET_LA>,
<&bpmp TEGRA234_RESET_HWPM>;
reset-names = "la", "hwpm";
iommus = <&smmu_niso1 TEGRA234_SID_HWMP_PMA>;
status = "okay";
};
pva0: pva0@16000000 {
compatible = "nvidia,tegra234-pva";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>;
reg = <0x16000000 0x800000>,
<0x24700000 0x080000>;
interrupts = <0 234 0x04>,
<0 432 0x04>,
<0 433 0x04>,
<0 434 0x04>,
<0 435 0x04>,
<0 436 0x04>,
<0 437 0x04>,
<0 438 0x04>,
<0 439 0x04>;
resets = <&bpmp TEGRA234_RESET_PVA0_ALL>;
clocks = <&bpmp TEGRA234_CLK_PVA0_CPU_AXI>,
<&bpmp TEGRA234_CLK_NAFLL_PVA0_VPS>,
<&bpmp TEGRA234_CLK_PVA0_VPS>;
clock-names = "axi", "vps0", "vps1";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0>;
dma-coherent;
status = "okay";
pva0_ctx0n1: pva0_niso1_ctx0 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM0>;
dma-coherent;
status = "okay";
};
pva0_ctx1n1: pva0_niso1_ctx1 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM1>;
dma-coherent;
status = "okay";
};
pva0_ctx2n1: pva0_niso1_ctx2 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM2>;
dma-coherent;
status = "okay";
};
pva0_ctx3n1: pva0_niso1_ctx3 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM3>;
dma-coherent;
status = "okay";
};
pva0_ctx4n1: pva0_niso1_ctx4 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM4>;
dma-coherent;
status = "okay";
};
pva0_ctx5n1: pva0_niso1_ctx5 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM5>;
dma-coherent;
status = "okay";
};
pva0_ctx6n1: pva0_niso1_ctx6 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM6>;
dma-coherent;
status = "okay";
};
pva0_ctx7n1: pva0_niso1_ctx7 {
compatible = "nvidia,pva-tegra186-iommu-context";
iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM7>;
dma-coherent;
status = "okay";
};
};
};
};
fragment-t234@2 {
target-path = "/";
__overlay__ {
aliases {
serial1 = "/bus@0/serial@3110000";
i2c0 = "/bus@0/i2c@3160000";
i2c1 = "/bus@0/i2c@c240000";
i2c2 = "/bus@0/i2c@3180000";
i2c3 = "/bus@0/i2c@3190000";
i2c4 = "/bpmp/i2c";
i2c5 = "/bus@0/i2c@31b0000";
i2c6 = "/bus@0/i2c@31c0000";
i2c7 = "/bus@0/i2c@c250000";
i2c8 = "/bus@0/i2c@31e0000";
};
};
};
fragment-t234@3 {
target-path = "/";
__overlay__ {
tegra_mce@e100000 {
compatible = "nvidia,t23x-mce";
reg = <0x0 0x0E100000 0x0 0x00010000>, /* ARI BASE Core 0*/
<0x0 0x0E110000 0x0 0x00010000>,
<0x0 0x0E120000 0x0 0x00010000>,
<0x0 0x0E130000 0x0 0x00010000>,
<0x0 0x0E140000 0x0 0x00010000>,
<0x0 0x0E150000 0x0 0x00010000>,
<0x0 0x0E160000 0x0 0x00010000>,
<0x0 0x0E170000 0x0 0x00010000>,
<0x0 0x0E180000 0x0 0x00010000>,
<0x0 0x0E190000 0x0 0x00010000>,
<0x0 0x0E1A0000 0x0 0x00010000>,
<0x0 0x0E1B0000 0x0 0x00010000>;
status = "okay";
};
};
};
fragment-t234@4 {
target-path = "/";
__overlay__ {
scf-pmu {
compatible = "nvidia,scf-pmu";
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0_0>;
status = "okay";
};
};
};
fragment-t234@6 {
target-path = "/bus@0/pwm@3280000";
__overlay__ {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
status = "okay";
};
};
fragment-t234@7 {
target-path = "/bus@0";
__overlay__ {
pwm2: pwm@3290000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x3290000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM2>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM2>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm3: pwm@32a0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32a0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM3>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM3>;
reset-names = "pwm";
status = "okay";
#pwm-cells = <2>;
};
pwm4: pwm@c340000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0xc340000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM4>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM4>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm5: pwm@32c0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32c0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM5>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM5>;
reset-names = "pwm";
status = "okay";
#pwm-cells = <2>;
};
pwm6: pwm@32d0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32d0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM6>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM6>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm7: pwm@32e0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32e0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM7>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM7>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm8: pwm@32f0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32f0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM8>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM8>;
reset-names = "pwm";
status = "okay";
#pwm-cells = <2>;
};
};
};
fragment-t234@8 {
target-path = "/";
__overlay__ {
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm3 0 45334>;
cooling-levels = <0 64 128 255>;
#cooling-cells = <2>;
};
};
};
fragment-t234@9 {
target-path = "/bus@0/pmc@c360000";
__overlay__ {
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <1>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <0>;
};
sdmmc3_3v3: sdmmc3-3v3 {
pins = "sdmmc3-hv";
power-source = <1>;
};
sdmmc3_1v8: sdmmc3-1v8 {
pins = "sdmmc3-hv";
power-source = <0>;
};
};
};
};