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nvethernet:Move blocking MACSec in PHY to server

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Removed the below functionality from Linux OSD as we moved
the same to ethernet server to avoid implementation in QNX OSD

- Restrict enabling MACSec in PHY

Bug 5221921

Change-Id: I0cbdeccfe91a67060a4609b9b8bc2bf842547b99
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3341020
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sanath Kumar Gampa
2025-04-15 05:15:30 -07:00
committed by Jon Hunter
parent d3e0d8bb36
commit 7fec719a7c
2 changed files with 0 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
drivers/net/ethernet/nvidia/nvethernet/ether_linux.c
View File

@@ -2900,26 +2900,6 @@ static int ether_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
"%s:No clks available, skipping PHY write\n", __func__); "%s:No clks available, skipping PHY write\n", __func__);
return -ENODEV; return -ENODEV;
} }
if (pdata->phy_str != NULL) {
// For MV-Q3244 0x401e002a is pointing to 0x407C2780 value pointed by Sau Loh from Mrvl
if (strcmp(pdata->phy_str, "MVQ3244") == 0) {
if ((phyreg == MACSEC_REG_MVQ3244) && ((phydata & OSI_BIT(1)) == 0U)) {
dev_err(pdata->dev,
"restricting access to enable macsec in MVQ3244 PHY \n");
return -ENODEV;
}
// For 88Q2221M dev 0x1F and Register 0xa008 is pointed to 0x401fa008
} else if (strcmp(pdata->phy_str, "88Q2221M") == 0) {
if ((phyaddr == MACSEC_REG_88Q2221M) &&
(((phydata & OSI_BIT(5)) == 0U) || ((phydata & OSI_BIT(6)) == 0U))) {
dev_err(pdata->dev,
"restricting access to enable macsec in 88Q221M PHY \n");
return -ENODEV;
}
} else {
/** Do Nothing for other PHY types */
}
}
return osi_write_phy_reg(pdata->osi_core, (unsigned int)phyaddr, return osi_write_phy_reg(pdata->osi_core, (unsigned int)phyaddr,
(unsigned int)phyreg, phydata); (unsigned int)phyreg, phydata);
@@ -4371,29 +4351,6 @@ static int ether_handle_priv_wmdio_ioctl(struct ether_priv_data *pdata,
prtad = mdio_phy_id_prtad(mii_data->phy_id); prtad = mdio_phy_id_prtad(mii_data->phy_id);
devad = mdio_phy_id_devad(mii_data->phy_id); devad = mdio_phy_id_devad(mii_data->phy_id);
devad = ether_mdio_c45_addr(devad, mii_data->reg_num); devad = ether_mdio_c45_addr(devad, mii_data->reg_num);
if (pdata->phy_str != NULL) {
// For MV-Q3244 0x401e002a is pointing to 0x407C2780 value pointed by Sau Loh from Mrvl
if (strcmp(pdata->phy_str, "MVQ3244") == 0) {
if ((devad == MACSEC_REG_MVQ3244) &&
((mii_data->val_in & OSI_BIT(1)) == 0U)) {
dev_err(pdata->dev,
"restricting access to enable macsec in MVQ3244 PHY \n");
return -ENODEV;
}
// For 88Q2221M dev 0x1F and Register 0xa008 is pointed to 0x401fa008
} else if (strcmp(pdata->phy_str, "88Q2221M") == 0) {
if ((devad == MACSEC_REG_88Q2221M) &&
(((mii_data->val_in & OSI_BIT(5)) == 0U) ||
((mii_data->val_in & OSI_BIT(6)) == 0U))) {
dev_err(pdata->dev,
"restricting access to enable macsec in 88Q2221M PHY \n");
return -ENODEV;
}
} else {
/** Do Nothing for other PHY types */
}
}
} else { } else {
prtad = mii_data->phy_id; prtad = mii_data->phy_id;
devad = mii_data->reg_num; devad = mii_data->reg_num;
@@ -7482,9 +7439,6 @@ int ether_probe(struct platform_device *pdev)
} }
} }
/* Read PHY type from DT */
(void)of_property_read_string(pdata->dev->of_node,
"nvidia,phy_type", &pdata->phy_str);
/* Set netdev features based on hw features */ /* Set netdev features based on hw features */
ether_set_ndev_features(ndev, pdata); ether_set_ndev_features(ndev, pdata);

8
drivers/net/ethernet/nvidia/nvethernet/ether_linux.h
View File

@@ -264,12 +264,6 @@
*/ */
#define FIXED_PHY_INVALID_MDIO_ADDR 0xFFU #define FIXED_PHY_INVALID_MDIO_ADDR 0xFFU
/**
* @brief PHY register address to enable MACSEc feature in PHY
*/
#define MACSEC_REG_MVQ3244 0x401e002aU
#define MACSEC_REG_88Q2221M 0x401fa008U
#define ETHER_ADDRESS_32BIT 0 #define ETHER_ADDRESS_32BIT 0
#define ETHER_ADDRESS_40BIT 1 #define ETHER_ADDRESS_40BIT 1
#define ETHER_ADDRESS_48BIT 2 #define ETHER_ADDRESS_48BIT 2
@@ -691,8 +685,6 @@ struct ether_priv_data {
int phy_reset_post_delay; int phy_reset_post_delay;
/** PHY reset duration delay */ /** PHY reset duration delay */
int phy_reset_duration; int phy_reset_duration;
/** Pointer to the phy type being used */
const char *phy_str;
#ifdef ETHER_NVGRO #ifdef ETHER_NVGRO
/** Master queue */ /** Master queue */
struct sk_buff_head mq; struct sk_buff_head mq;