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gpu: host1x-nvhost: avoid setting flcn irq at boot

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[1] The DLA firmware configures the DEST and MASK registers during
    the initialization.
[2] In OOT, the DLA KMD is accidentally setting the interrupts. This
    will result in enabling additional interrupts that the firmware
    does not handle (like NVDLA_GENERIC_INTR_FAULT_CRITICAL).
[3] This commit fixes the issue by avoiding the interrupt settings
    at the DLA KMD.

Bug 3960841

Change-Id: Ied77ac7564ae3b3202b9cceaf08ad3c7da9f947c
Signed-off-by: Arvind M <am@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2861253
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Arvind M
2023-02-21 11:23:37 +00:00
committed by Laxman Dewangan
parent bc86b17fa2
commit 8942623b15
1 changed files with 1 additions and 16 deletions
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17
drivers/gpu/host1x-nvhost/falcon.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2022, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2015-2023, NVIDIA Corporation. All rights reserved.
*/
#include <linux/platform_device.h>
@@ -182,21 +182,6 @@ int falcon_boot(struct falcon *falcon)
falcon_copy_chunk(falcon, falcon->firmware.code.offset + offset,
offset, FALCON_MEMORY_IMEM);
/* setup falcon interrupts */
falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) |
FALCON_IRQMSET_SWGEN1 |
FALCON_IRQMSET_SWGEN0 |
FALCON_IRQMSET_EXTERR |
FALCON_IRQMSET_HALT |
FALCON_IRQMSET_WDTMR,
FALCON_IRQMSET);
falcon_writel(falcon, FALCON_IRQDEST_EXT(0xff) |
FALCON_IRQDEST_SWGEN1 |
FALCON_IRQDEST_SWGEN0 |
FALCON_IRQDEST_EXTERR |
FALCON_IRQDEST_HALT,
FALCON_IRQDEST);
/* enable interface */
falcon_writel(falcon, FALCON_ITFEN_MTHDEN |
FALCON_ITFEN_CTXEN,