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ASoC: tegra-alt: Add default reg values

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Set default register values for AHUB modules in regmap. This will
ensure after runtime suspend/resume AHUB register POR values
does not get reset to 0.

Bug 200039212

Change-Id: I38e4c04721450b7511404c0db2911b314b68a880
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/603339
This commit is contained in:
Sumit Bhattacharya
2014-11-11 22:20:42 +05:30
committed by Sameer Pujar
parent 3186618fae
commit 8f8c3d0aa9
14 changed files with 266 additions and 0 deletions
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25
sound/soc/tegra-alt/tegra210_admaif_alt.c
View File

@@ -36,6 +36,29 @@
#define DRV_NAME "tegra210-ape-admaif"
#define ADMAIF_CH_REG(reg, id) (reg + (TEGRA210_ADMAIF_CHANNEL_REG_STRIDE * id))
#define ADMAIF_REG_DEFAULTS(id, rx_fifo_ctrl, tx_fifo_ctrl) \
{ ADMAIF_CH_REG(TEGRA210_ADMAIF_XBAR_RX_INT_MASK, id), 0x00000001}, \
{ ADMAIF_CH_REG(TEGRA210_ADMAIF_CHAN_ACIF_RX_CTRL, id), 0x00007700}, \
{ ADMAIF_CH_REG(TEGRA210_ADMAIF_XBAR_RX_FIFO_CTRL, id), rx_fifo_ctrl}, \
{ ADMAIF_CH_REG(TEGRA210_ADMAIF_XBAR_TX_INT_MASK, id), 0x00000001}, \
{ ADMAIF_CH_REG(TEGRA210_ADMAIF_CHAN_ACIF_TX_CTRL, id), 0x00007700}, \
{ ADMAIF_CH_REG(TEGRA210_ADMAIF_XBAR_TX_FIFO_CTRL, id), tx_fifo_ctrl}
static const struct reg_default tegra210_admaif_reg_defaults[] = {
ADMAIF_REG_DEFAULTS(0, 0x00000300, 0x02000300),
ADMAIF_REG_DEFAULTS(1, 0x00000304, 0x02000304),
ADMAIF_REG_DEFAULTS(2, 0x00000208, 0x01800208),
ADMAIF_REG_DEFAULTS(3, 0x0000020b, 0x0180020b),
ADMAIF_REG_DEFAULTS(4, 0x0000020e, 0x0180020e),
ADMAIF_REG_DEFAULTS(5, 0x00000211, 0x01800211),
ADMAIF_REG_DEFAULTS(6, 0x00000214, 0x01800214),
ADMAIF_REG_DEFAULTS(7, 0x00000217, 0x01800217),
ADMAIF_REG_DEFAULTS(8, 0x0000021a, 0x0180021a),
ADMAIF_REG_DEFAULTS(9, 0x0000021d, 0x0180021d),
{ TEGRA210_ADMAIF_GLOBAL_CG_0, 0x00000003}
};
static bool tegra210_admaif_wr_reg(struct device *dev, unsigned int reg)
{
reg = reg % TEGRA210_ADMAIF_CHANNEL_REG_STRIDE;
@@ -110,6 +133,8 @@ static const struct regmap_config tegra210_admaif_regmap_config = {
.writeable_reg = tegra210_admaif_wr_reg,
.readable_reg = tegra210_admaif_rd_reg,
.volatile_reg = tegra210_admaif_volatile_reg,
.reg_defaults = tegra210_admaif_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_admaif_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

14
sound/soc/tegra-alt/tegra210_adx_alt.c
View File

@@ -37,6 +37,18 @@
#define DRV_NAME "tegra210-adx"
static const struct reg_default tegra210_adx_reg_defaults[] = {
{ TEGRA210_ADX_AXBAR_RX_INT_MASK, 0x00000001},
{ TEGRA210_ADX_AXBAR_RX_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_AXBAR_TX_INT_MASK, 0x0000000f },
{ TEGRA210_ADX_AXBAR_TX1_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_AXBAR_TX2_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_AXBAR_TX3_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_AXBAR_TX4_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_CG, 0x1},
{ TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, 0x00004000},
};
/**
* tegra210_adx_enable_outstream - enable output stream
* @adx: struct of tegra210_adx
@@ -604,6 +616,8 @@ static const struct regmap_config tegra210_adx_regmap_config = {
.writeable_reg = tegra210_adx_wr_reg,
.readable_reg = tegra210_adx_rd_reg,
.volatile_reg = tegra210_adx_volatile_reg,
.reg_defaults = tegra210_adx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_adx_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

23
sound/soc/tegra-alt/tegra210_afc_alt.c
View File

@@ -37,6 +37,27 @@
#define DRV_NAME "tegra210-afc"
static const struct reg_default tegra210_afc_reg_defaults[] = {
{ TEGRA210_AFC_AXBAR_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_AFC_AXBAR_TX_INT_MASK, 0x00000001},
{ TEGRA210_AFC_AXBAR_TX_CIF_CTRL, 0x00007000},
{ TEGRA210_AFC_CG, 0x1},
{ TEGRA210_AFC_INT_MASK, 0x1},
{ TEGRA210_AFC_DEST_I2S_PARAMS, 0x01190e0c },
{ TEGRA210_AFC_TXCIF_FIFO_PARAMS, 0x00190e0c },
{ TEGRA210_AFC_CLK_PPM_DIFF, 0x0000001e},
{ TEGRA210_AFC_LCOEF_1_4_0, 0x0000002e},
{ TEGRA210_AFC_LCOEF_1_4_1, 0x0000f9e6},
{ TEGRA210_AFC_LCOEF_1_4_2, 0x000020ca},
{ TEGRA210_AFC_LCOEF_1_4_3, 0x00007147},
{ TEGRA210_AFC_LCOEF_1_4_4, 0x0000f17e},
{ TEGRA210_AFC_LCOEF_1_4_5, 0x000001e0},
{ TEGRA210_AFC_LCOEF_2_4_0, 0x00000117},
{ TEGRA210_AFC_LCOEF_2_4_1, 0x0000f26b},
{ TEGRA210_AFC_LCOEF_2_4_2, 0x00004c07},
};
static int tegra210_afc_runtime_suspend(struct device *dev)
{
struct tegra210_afc *afc = dev_get_drvdata(dev);
@@ -337,6 +358,8 @@ static const struct regmap_config tegra210_afc_regmap_config = {
.writeable_reg = tegra210_afc_wr_rd_reg,
.readable_reg = tegra210_afc_wr_rd_reg,
.volatile_reg = tegra210_afc_volatile_reg,
.reg_defaults = tegra210_afc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_afc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

14
sound/soc/tegra-alt/tegra210_amx_alt.c
View File

@@ -37,6 +37,18 @@
#define DRV_NAME "tegra210-amx"
static const struct reg_default tegra210_amx_reg_defaults[] = {
{ TEGRA210_AMX_AXBAR_RX_INT_MASK, 0x0000000f},
{ TEGRA210_AMX_AXBAR_RX1_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_AXBAR_RX2_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_AXBAR_RX3_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_AXBAR_RX4_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_AXBAR_TX_INT_MASK, 0x00000001},
{ TEGRA210_AMX_AXBAR_TX_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_CG, 0x1},
{ TEGRA210_AMX_AHUBRAMCTL_AMX_CTRL, 0x00004000},
};
/**
* tegra210_amx_set_master_stream - set master stream and dependency
* @amx: struct of tegra210_amx
@@ -637,6 +649,8 @@ static const struct regmap_config tegra210_amx_regmap_config = {
.writeable_reg = tegra210_amx_wr_reg,
.readable_reg = tegra210_amx_rd_reg,
.volatile_reg = tegra210_amx_volatile_reg,
.reg_defaults = tegra210_amx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

32
sound/soc/tegra-alt/tegra210_dmic_alt.c
View File

@@ -37,6 +37,36 @@
#define DRV_NAME "tegra210-dmic"
static const struct reg_default tegra210_dmic_reg_defaults[] = {
{ TEGRA210_DMIC_TX_INT_MASK, 0x00000001},
{ TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_DMIC_CG, 0x1},
{ TEGRA210_DMIC_CTRL, 0x00000301},
{ TEGRA210_DMIC_DCR_FILTER_GAIN, 0x00800000},
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_0, 0x00800000},
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_1, 0xff800000},
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_3, 0xff800347},
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0xffc0ff97},
{ TEGRA210_DMIC_LP_FILTER_GAIN, 0x004c255a},
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000},
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x00ffa74b},
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x00800000},
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x009e382a},
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x00380f38},
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000},
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x00fe1178},
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x00800000},
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x00e05f02},
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x006fc80d},
{ TEGRA210_DMIC_CORRECTION_FILTER_GAIN, 0x010628f6},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_0, 0x00800000},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_3, 0x0067ffff},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_0, 0x00800000},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_1, 0x0048f5c2},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_3, 0x00562394},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4, 0x00169446},
};
static int tegra210_dmic_runtime_suspend(struct device *dev)
{
struct tegra210_dmic *dmic = dev_get_drvdata(dev);
@@ -290,6 +320,8 @@ static const struct regmap_config tegra210_dmic_regmap_config = {
.readable_reg = tegra210_dmic_rd_reg,
.volatile_reg = tegra210_dmic_volatile_reg,
.precious_reg = NULL,
.reg_defaults = tegra210_dmic_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_dmic_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

11
sound/soc/tegra-alt/tegra210_i2s_alt.c
View File

@@ -42,6 +42,15 @@
#define DRV_NAME "tegra210-i2s"
static const struct reg_default tegra210_i2s_reg_defaults[] = {
{ TEGRA210_I2S_AXBAR_RX_INT_MASK, 0x00000003},
{ TEGRA210_I2S_AXBAR_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_I2S_AXBAR_TX_INT_MASK, 0x00000003},
{ TEGRA210_I2S_AXBAR_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_I2S_CG, 0x1},
{ TEGRA210_I2S_TIMING, 0x0000001f},
};
static void tegra210_i2s_set_slot_ctrl(struct regmap *regmap,
unsigned int total_slots,
unsigned int tx_slot_mask,
@@ -741,6 +750,8 @@ static const struct regmap_config tegra210_i2s_regmap_config = {
.writeable_reg = tegra210_i2s_wr_reg,
.readable_reg = tegra210_i2s_rd_reg,
.volatile_reg = tegra210_i2s_volatile_reg,
.reg_defaults = tegra210_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_i2s_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

9
sound/soc/tegra-alt/tegra210_iqc_alt.c
View File

@@ -37,6 +37,13 @@
#define DRV_NAME "tegra210-iqc"
static const struct reg_default tegra210_iqc_reg_defaultss[] = {
{ TEGRA210_IQC_AXBAR_TX_INT_MASK, 0x0000000f},
{ TEGRA210_IQC_AXBAR_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_IQC_CG, 0x1},
{ TEGRA210_IQC_CTRL, 0x80000020},
};
static int tegra210_iqc_runtime_suspend(struct device *dev)
{
struct tegra210_iqc *iqc = dev_get_drvdata(dev);
@@ -307,6 +314,8 @@ static const struct regmap_config tegra210_iqc_regmap_config = {
.writeable_reg = tegra210_iqc_wr_reg,
.readable_reg = tegra210_iqc_rd_reg,
.volatile_reg = tegra210_iqc_volatile_reg,
.reg_defaults = tegra210_iqc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_iqc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

33
sound/soc/tegra-alt/tegra210_mbdrc_alt.c
View File

@@ -29,6 +29,37 @@
#include "tegra210_ope_alt.h"
#include "tegra210_mbdrc_alt.h"
#define MBDRC_FILTER_REG(reg, id) \
(reg + (id * TEGRA210_MBDRC_FILTER_PARAM_STRIDE))
#define MBDRC_FILTER_REG_DEFAULTS(id) \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IIR_CONFIG, id), 0x00000005}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_ATTACK, id), 0x3e48590c}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_RELEASE, id), 0x08414e9f}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_ATTACK, id), 0x7fffffff}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_THRESHOLD, id), 0x06145082}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_OUT_THRESHOLD, id), 0x060d379b}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_1ST, id), 0x0000a000}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_2ND, id), 0x00002000}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_3RD, id), 0x00000b33}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_4TH, id), 0x00000800}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_5TH, id), 0x0000019a}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_MAKEUP_GAIN, id), 0x00000002}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_INIT_GAIN, id), 0x00066666}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_ATTACK, id), 0x00d9ba0e}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_RELEASE, id), 0x3e48590c}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_RELEASE, id), 0x7ffff26a}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_AHUBRAMCTL_CONFIG_RAM_CTRL, id), 0x4000}
static const struct reg_default tegra210_mbdrc_reg_defaults[] = {
{ TEGRA210_MBDRC_CONFIG, 0x0030de51},
{ TEGRA210_MBDRC_CHANNEL_MASK, 0x00000003},
{ TEGRA210_MBDRC_FAST_FACTOR, 0x30000800},
MBDRC_FILTER_REG_DEFAULTS(0),
MBDRC_FILTER_REG_DEFAULTS(1),
MBDRC_FILTER_REG_DEFAULTS(2)
};
/* Default MBDRC parameters */
static const struct tegra210_mbdrc_config mbdrc_init_config = {
.mode = 0, /* bypass */
@@ -579,6 +610,8 @@ static const struct regmap_config tegra210_mbdrc_regmap_config = {
.readable_reg = tegra210_mbdrc_rd_reg,
.volatile_reg = tegra210_mbdrc_volatile_reg,
.precious_reg = tegra210_mbdrc_precious_reg,
.reg_defaults = tegra210_mbdrc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_mbdrc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

37
sound/soc/tegra-alt/tegra210_mixer_alt.c
View File

@@ -36,10 +36,45 @@
#define DRV_NAME "tegra210_mixer"
#define MIXER_RX_REG(reg, id) (reg + (id * TEGRA210_MIXER_AXBAR_RX_STRIDE))
#define MIXER_TX_REG(reg, id) (reg + (id * TEGRA210_MIXER_AXBAR_TX_STRIDE))
#define MIXER_GAIN_CONFIG_RAM_ADDR(id) \
(TEGRA210_MIXER_AHUBRAMCTL_GAIN_CONFIG_RAM_ADDR_0 + \
id*TEGRA210_MIXER_AHUBRAMCTL_GAIN_CONFIG_RAM_ADDR_STRIDE)
#define MIXER_RX_REG_DEFAULTS(id) \
{ MIXER_RX_REG(TEGRA210_MIXER_AXBAR_RX1_CIF_CTRL, id), 0x00007700}, \
{ MIXER_RX_REG(TEGRA210_MIXER_AXBAR_RX1_CTRL, id), 0x00010823}, \
{ MIXER_RX_REG(TEGRA210_MIXER_AXBAR_RX1_PEAK_CTRL, id), 0x000012c0}
#define MIXER_TX_REG_DEFAULTS(id) \
{ MIXER_TX_REG(TEGRA210_MIXER_AXBAR_TX1_INT_MASK, id), 0x00000001}, \
{ MIXER_TX_REG(TEGRA210_MIXER_AXBAR_TX1_CIF_CTRL, id), 0x00007700}
static const struct reg_default tegra210_mixer_reg_defaults[] = {
MIXER_RX_REG_DEFAULTS(0),
MIXER_RX_REG_DEFAULTS(1),
MIXER_RX_REG_DEFAULTS(2),
MIXER_RX_REG_DEFAULTS(3),
MIXER_RX_REG_DEFAULTS(4),
MIXER_RX_REG_DEFAULTS(5),
MIXER_RX_REG_DEFAULTS(6),
MIXER_RX_REG_DEFAULTS(7),
MIXER_RX_REG_DEFAULTS(8),
MIXER_RX_REG_DEFAULTS(9),
MIXER_TX_REG_DEFAULTS(0),
MIXER_TX_REG_DEFAULTS(1),
MIXER_TX_REG_DEFAULTS(2),
MIXER_TX_REG_DEFAULTS(3),
MIXER_TX_REG_DEFAULTS(4),
{ TEGRA210_MIXER_CG, 0x00000001},
{ TEGRA210_MIXER_AHUBRAMCTL_GAIN_CONFIG_RAM_CTRL, 0x00004000},
{ TEGRA210_MIXER_AHUBRAMCTL_PEAKM_RAM_CTRL, 0x00004000},
};
static int tegra210_mixer_runtime_suspend(struct device *dev)
{
struct tegra210_mixer *mixer = dev_get_drvdata(dev);
@@ -536,6 +571,8 @@ static const struct regmap_config tegra210_mixer_regmap_config = {
.readable_reg = tegra210_mixer_rd_reg,
.volatile_reg = tegra210_mixer_volatile_reg,
.precious_reg = tegra210_mixer_precious_reg,
.reg_defaults = tegra210_mixer_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_mixer_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

19
sound/soc/tegra-alt/tegra210_mvc_alt.c
View File

@@ -36,6 +36,23 @@
#define DRV_NAME "tegra210-mvc"
static const struct reg_default tegra210_mvc_reg_defaults[] = {
{ TEGRA210_MVC_AXBAR_RX_INT_MASK, 0x00000001},
{ TEGRA210_MVC_AXBAR_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_MVC_AXBAR_TX_INT_MASK, 0x00000001},
{ TEGRA210_MVC_AXBAR_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_MVC_CG, 0x1},
{ TEGRA210_MVC_CTRL, 0x40000001},
{ TEGRA210_MVC_INIT_VOL, 0x00800000},
{ TEGRA210_MVC_TARGET_VOL, 0x00800000},
{ TEGRA210_MVC_DURATION, 0x000012c0},
{ TEGRA210_MVC_DURATION_INV, 0x0006d3a0},
{ TEGRA210_MVC_POLY_N1, 0x0000007d},
{ TEGRA210_MVC_POLY_N2, 0x00000271},
{ TEGRA210_MVC_PEAK_CTRL, 0x000012c0},
{ TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL, 0x00004000},
};
static int tegra210_mvc_runtime_suspend(struct device *dev)
{
struct tegra210_mvc *mvc = dev_get_drvdata(dev);
@@ -380,6 +397,8 @@ static const struct regmap_config tegra210_mvc_regmap_config = {
.writeable_reg = tegra210_mvc_wr_rd_reg,
.readable_reg = tegra210_mvc_wr_rd_reg,
.volatile_reg = tegra210_mvc_volatile_reg,
.reg_defaults = tegra210_mvc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_mvc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

10
sound/soc/tegra-alt/tegra210_ope_alt.c
View File

@@ -37,6 +37,14 @@
#define DRV_NAME "tegra210-ope"
static const struct reg_default tegra210_ope_reg_defaults[] = {
{ TEGRA210_OPE_AXBAR_RX_INT_MASK, 0x00000001},
{ TEGRA210_OPE_AXBAR_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_OPE_AXBAR_TX_INT_MASK, 0x00000001},
{ TEGRA210_OPE_AXBAR_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_OPE_CG, 0x1},
};
static int tegra210_ope_runtime_suspend(struct device *dev)
{
struct tegra210_ope *ope = dev_get_drvdata(dev);
@@ -302,6 +310,8 @@ static const struct regmap_config tegra210_ope_regmap_config = {
.writeable_reg = tegra210_ope_wr_reg,
.readable_reg = tegra210_ope_rd_reg,
.volatile_reg = tegra210_ope_volatile_reg,
.reg_defaults = tegra210_ope_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_ope_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

8
sound/soc/tegra-alt/tegra210_peq_alt.c
View File

@@ -36,6 +36,12 @@
#include "tegra210_ope_alt.h"
#include "tegra210_peq_alt.h"
static const struct reg_default tegra210_peq_reg_defaults[] = {
{ TEGRA210_PEQ_CONFIG, 0x00000013},
{ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL, 0x00004000},
{ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL, 0x00004000},
};
/* Default PEQ filter parameters for a 5-stage biquad*/
static const int biquad_init_stage = 5;
static const u32 biquad_init_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH] = {
@@ -225,6 +231,8 @@ static const struct regmap_config tegra210_peq_regmap_config = {
.readable_reg = tegra210_peq_rd_reg,
.volatile_reg = tegra210_peq_volatile_reg,
.precious_reg = tegra210_peq_precious_reg,
.reg_defaults = tegra210_peq_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_peq_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

11
sound/soc/tegra-alt/tegra210_sfc_alt.c
View File

@@ -36,6 +36,15 @@
#define DRV_NAME "tegra210-sfc"
static const struct reg_default tegra210_sfc_reg_defaults[] = {
{ TEGRA210_SFC_AXBAR_RX_INT_MASK, 0x00000001},
{ TEGRA210_SFC_AXBAR_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_SFC_AXBAR_TX_INT_MASK, 0x00000001},
{ TEGRA210_SFC_AXBAR_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_SFC_CG, 0x1},
{ TEGRA210_SFC_AHUBRAMCTL_SFC_CTRL, 0x00004000},
};
static int tegra210_sfc_runtime_suspend(struct device *dev)
{
struct tegra210_sfc *sfc = dev_get_drvdata(dev);
@@ -438,6 +447,8 @@ static const struct regmap_config tegra210_sfc_regmap_config = {
.readable_reg = tegra210_sfc_rd_reg,
.volatile_reg = tegra210_sfc_volatile_reg,
.precious_reg = tegra210_sfc_precious_reg,
.reg_defaults = tegra210_sfc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_sfc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};

20
sound/soc/tegra-alt/tegra210_spdif_alt.c
View File

@@ -36,6 +36,24 @@
#define DRV_NAME "tegra210-spdif"
static const struct reg_default tegra210_spdif_reg_defaults[] = {
{ TEGRA210_SPDIF_CIF_TXD_CTRL, 0x00001100},
{ TEGRA210_SPDIF_CIF_RXD_CTRL, 0x00001100},
{ TEGRA210_SPDIF_CIF_TXU_CTRL, 0x00001100},
{ TEGRA210_SPDIF_CIF_RXU_CTRL, 0x00001100},
{ TEGRA210_SPDIF_FLOWCTL_CTRL, 0x80000000},
{ TEGRA210_SPDIF_TX_STEP, 0x00008000},
{ TEGRA210_SPDIF_LCOEF_1_4_0, 0x0000002e},
{ TEGRA210_SPDIF_LCOEF_1_4_1, 0x0000f9e6},
{ TEGRA210_SPDIF_LCOEF_1_4_2, 0x000020ca},
{ TEGRA210_SPDIF_LCOEF_1_4_3, 0x00007147},
{ TEGRA210_SPDIF_LCOEF_1_4_4, 0x0000f17e},
{ TEGRA210_SPDIF_LCOEF_1_4_5, 0x000001e0},
{ TEGRA210_SPDIF_LCOEF_2_4_0, 0x00000117},
{ TEGRA210_SPDIF_LCOEF_2_4_1, 0x0000f26b},
{ TEGRA210_SPDIF_LCOEF_2_4_2, 0x00004c07},
};
static int tegra210_spdif_runtime_suspend(struct device *dev)
{
struct tegra210_spdif *spdif = dev_get_drvdata(dev);
@@ -334,6 +352,8 @@ static const struct regmap_config tegra210_spdif_regmap_config = {
.max_register = TEGRA210_SPDIF_LCOEF_2_4_2,
.writeable_reg = tegra210_spdif_wr_rd_reg,
.readable_reg = tegra210_spdif_wr_rd_reg,
.reg_defaults = tegra210_spdif_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_spdif_reg_defaults),
.cache_type = REGCACHE_FLAT,
};