r8126: Disable LTR_EN in PCIe DevCtl2 register during probe

Problem:
- When a Downstream Port Containment (DPC) software trigger is issued, the LTR_EN bit in the Root Port (RP) is cleared as per PCIe spec.
- However, LTR_EN bit of RTL8126 endpoint (EP) which is being expected to reset is still active and sends Latency Tolerance Reports (LTR) to RP.
- This behavior violates the PCIe spec, as LTR_EN is a non-sticky bit and should be cleared automatically on reset.
- As the RP has LTR disabled but the EP still sends LTR messages, it results in Unsupported Request (UR) errors on the RP.
- These UR errors trigger AER (Advanced Error Reporting) recovery, which includes a Secondary Bus Reset (SBR).
- The SBR causes the PCIe link to go down and come back up, but the EP again starts sending LTRs, leading to a infinite error-recovery loop.

Workaround:
- As a temporary fix, disable the LTR_EN bit in the RTL8126 EP during its probe.
- This prevents the EP from sending LTR messages, thereby avoiding UR errors and breaking the loop of AER recovery.

Impact:
- Disabling LTR prevents the EP from entering the L1.2 low power state.
- However, ASPM is currently not enabled in the system, so this workaround has no impact.

Bug 4869463

Change-Id: Ibf7effaeb0f22e952645ef7bf6a18287264e1463
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3420019
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>

drivers/net/ethernet/realtek/r8126/r8126.h

@@ -35,7 +35,7 @@
 #ifndef __R8126_H
 #define __R8126_H
 
-//#include <linux/pci.h>
+#include <linux/pci.h>
 #include <linux/ethtool.h>
 #include <linux/interrupt.h>
 #include <linux/version.h>

drivers/net/ethernet/realtek/r8126/r8126_n.c

@@ -14405,6 +14405,9 @@ rtl8126_init_one(struct pci_dev *pdev,
         tp = netdev_priv(dev);
         assert(ioaddr != NULL);
 
+	/* Disable LTR_EN bit in DevCtl2 register of RTL Endpoint */
+	pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);
+
         spin_lock_init(&tp->phy_lock);
 
         tp->set_speed = rtl8126_set_speed_xmii;