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platform: dce: Add t264 halify function support
This patch moves T264 files to nvidia-oot repo and adds support to to Halify HSP functions for T239. Jira TDS-15438 Change-Id: Ie42d15ab27f9a71312063a4067629030be6869c8 Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3233122 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahesh Kumar
@@ -1,35 +1,42 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#
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# Display Controller Engine code.
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#
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GCOV_PROFILE := y
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ccflags-y += -I$(srctree.nvidia-oot)/drivers/platform/tegra/dce/include
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ccflags-y += -Werror
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ifeq ($(CONFIG_TEGRA_OOT_MODULE),m)
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CONFIG_TEGRA_DCE := m
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else # CONFIG_TEGRA_OOT_MODULE
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CONFIG_TEGRA_DCE := y
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endif # CONFIG_TEGRA_OOT_MODULE
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obj-m += tegra-dce.o
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tegra-dce-objs += \
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dce-ast.o \
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dce-reset.o \
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dce-hsp-smb.o \
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dce-hsp-ss.o \
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dce-worker.o \
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dce-fsm.o \
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dce-init-deinit.o \
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dce-mailbox.o \
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dce-bootstrap.o \
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dce-admin.o \
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dce-ipc.o \
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dce-ipc-signal.o \
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dce-client-ipc.o \
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dce-module.o \
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dce-pm.o \
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dce-util-common.o
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ccflags-y += -I$(srctree.nvidia-oot)/include
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ccflags-y += -I$(srctree.nvidia-oot)/drivers/platform/tegra/dce/include
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obj-$(CONFIG_TEGRA_DCE) += tegra-dce.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-ast.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-reset.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-hsp-smb.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-hsp-ss.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-worker.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-fsm.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-init-deinit.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-mailbox.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-bootstrap.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-admin.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-ipc.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-ipc-signal.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-client-ipc.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-module.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-pm.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-util-common.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-hsp-smb-t264.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-hsp-ss-t264.o
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ifeq ($(CONFIG_DEBUG_FS),y)
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tegra-dce-objs += \
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dce-debug.o \
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dce-admin-debug.o \
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dce-debug-perf.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-debug.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-admin-debug.o
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tegra-dce-$(CONFIG_TEGRA_DCE) += dce-debug-perf.o
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endif
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312
drivers/platform/tegra/dce/dce-hsp-smb-t264.c
Normal file
312
drivers/platform/tegra/dce/dce-hsp-smb-t264.c
Normal file
@@ -0,0 +1,312 @@
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/*
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* Copyright (c) 2023-2024, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <dce.h>
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#include <dce-util-common.h>
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#include <hw/t264/hw_hsp_dce.h>
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#include <dce-hsp-t264.h>
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/**
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* smb_regs is a 2D array of read-only pointers to a function returning u32.
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*
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* Array of functions that retrun base addresses of shared maiboxes registers
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* in DCE cluster based on the mailbox id and HSP id.
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*/
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static u32 (*const smb_regs[DCE_MAX_HSP_T264][DCE_MAX_NO_SMB_T264])(void) = {
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[0U] = {
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hsp_0_sm0_r,
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hsp_0_sm1_r,
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hsp_0_sm2_r,
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hsp_0_sm3_r,
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hsp_0_sm4_r,
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hsp_0_sm5_r,
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hsp_0_sm6_r,
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hsp_0_sm7_r,
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},
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[1U] = {
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hsp_1_sm0_r,
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hsp_1_sm1_r,
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hsp_1_sm2_r,
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hsp_1_sm3_r,
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hsp_1_sm4_r,
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hsp_1_sm5_r,
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hsp_1_sm6_r,
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hsp_1_sm7_r,
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},
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};
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/**
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* smb_full_ie_regs is a 2D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of full IE for shared
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* maiboxes registers in DCE cluster based on the mailbox id and HSP id.
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*/
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static u32 (*const smb_full_ie_regs[DCE_MAX_HSP_T264][DCE_MAX_NO_SMB_T264])(void) = {
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[0U] = {
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hsp_0_sm0_full_int_ie_r,
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hsp_0_sm1_full_int_ie_r,
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hsp_0_sm2_full_int_ie_r,
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hsp_0_sm3_full_int_ie_r,
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hsp_0_sm4_full_int_ie_r,
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hsp_0_sm5_full_int_ie_r,
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hsp_0_sm6_full_int_ie_r,
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hsp_0_sm7_full_int_ie_r,
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},
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[1U] = {
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hsp_1_sm0_full_int_ie_r,
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hsp_1_sm1_full_int_ie_r,
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hsp_1_sm2_full_int_ie_r,
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hsp_1_sm3_full_int_ie_r,
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hsp_1_sm4_full_int_ie_r,
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hsp_1_sm5_full_int_ie_r,
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hsp_1_sm6_full_int_ie_r,
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hsp_1_sm7_full_int_ie_r,
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},
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};
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/**
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* smb_empty_ie_regs is a 2D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of empty IE for shared
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* maiboxes registers in DCE cluster based on the mailbox id and HSP id.
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*/
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static u32 (*const smb_empty_ie_regs[DCE_MAX_HSP_T264][DCE_MAX_NO_SMB_T264])(void) = {
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[0U] = {
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hsp_0_sm0_empty_int_ie_r,
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hsp_0_sm1_empty_int_ie_r,
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hsp_0_sm2_empty_int_ie_r,
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hsp_0_sm3_empty_int_ie_r,
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hsp_0_sm4_empty_int_ie_r,
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hsp_0_sm5_empty_int_ie_r,
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hsp_0_sm6_empty_int_ie_r,
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hsp_0_sm7_empty_int_ie_r,
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},
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[1U] = {
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hsp_1_sm0_empty_int_ie_r,
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hsp_1_sm1_empty_int_ie_r,
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hsp_1_sm2_empty_int_ie_r,
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hsp_1_sm3_empty_int_ie_r,
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hsp_1_sm4_empty_int_ie_r,
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hsp_1_sm5_empty_int_ie_r,
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hsp_1_sm6_empty_int_ie_r,
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hsp_1_sm7_empty_int_ie_r,
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},
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};
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/**
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* dce_smb_set_t264 - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @val : val to set.
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* @hsp_id : ID of hsp instance used
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* @id : Shared Mailbox Id.
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*
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* Return : Void
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*/
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void dce_smb_set_t264(struct tegra_dce *d, u32 val, u8 hsp_id, u8 id)
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{
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if (id >= DCE_MAX_NO_SMB_T264 || hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid Shared Mailbox ID:%u or hsp:%u", id, hsp_id);
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return;
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}
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dce_writel(d, smb_regs[hsp_id][id](), val);
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}
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/**
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* dce_smb_set_full_ie_t264 - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @en : enable if true and disable if false
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* @hsp_id : ID of hsp instance used
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* @id : Shared Mailbox Id.
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*
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* Return : Void
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*/
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void dce_smb_set_full_ie_t264(struct tegra_dce *d, bool en, u8 hsp_id, u8 id)
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{
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u32 val = en ? 1U : 0U;
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if (id >= DCE_MAX_NO_SMB_T264 || hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid Shared Mailbox ID:%u or hsp:%u", id, hsp_id);
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return;
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}
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dce_writel(d, smb_full_ie_regs[hsp_id][id](), val);
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}
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/**
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* dce_smb_read_full_ie_t264 - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @hsp_id : ID of hsp instance used
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* @id : Shared Mailbox Id.
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*
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* Return : u32 register value
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*/
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u32 dce_smb_read_full_ie_t264(struct tegra_dce *d, u8 hsp_id, u8 id)
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{
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if (id >= DCE_MAX_NO_SMB_T264 || hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid Shared Mailbox ID:%u or hsp:%u", id, hsp_id);
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return 0xffffffff; /* TODO : Add DCE Error Numbers */
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}
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return dce_readl(d, smb_full_ie_regs[hsp_id][id]());
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}
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/**
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* dce_smb_enable_empty_ie_t264 - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @en : enable if true and disable if false
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* @hsp_id : ID of hsp instance used
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* @id : Shared Mailbox Id.
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*
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* Return : Void
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*/
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void dce_smb_set_empty_ie_t264(struct tegra_dce *d, bool en, u8 hsp_id, u8 id)
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{
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u32 val = en ? 1U : 0U;
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if (id >= DCE_MAX_NO_SMB_T264 || hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid Shared Mailbox ID:%u or hsp:%u", id, hsp_id);
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return;
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}
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dce_writel(d, smb_empty_ie_regs[hsp_id][id](), val);
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}
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/**
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* dce_smb_read_t264 - Read the u32 value from smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @hsp_id : ID of hsp instance used
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* @id : Shared Mailbox Id.
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*
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* Return : actual value if successful, 0xffffffff for errors scenarios
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*/
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u32 dce_smb_read_t264(struct tegra_dce *d, u8 hsp_id, u8 id)
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{
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if (id >= DCE_MAX_NO_SMB_T264 || hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid Shared Mailbox ID:%u or hsp:%u", id, hsp_id);
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return 0xffffffff; /* TODO : Add DCE Error Numbers */
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}
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return dce_readl(d, smb_regs[hsp_id][id]());
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}
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/**
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* hsp_int_ie_regs is a 2D array of read-only pointers to a
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* function returning u32.
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*
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* Array of functions that retrun base addresses of hsp IE
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* regs in DCE cluster based on the id.
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*/
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static u32 (*const hsp_int_ie_regs[DCE_MAX_HSP_T264][DCE_MAX_NO_SMB_T264])(void) = {
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[0U] = {
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hsp_0_int_ie0_r,
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hsp_0_int_ie1_r,
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hsp_0_int_ie2_r,
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hsp_0_int_ie3_r,
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hsp_0_int_ie4_r,
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hsp_0_int_ie5_r,
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hsp_0_int_ie6_r,
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hsp_0_int_ie7_r,
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},
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[1U] = {
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hsp_1_int_ie0_r,
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hsp_1_int_ie1_r,
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hsp_1_int_ie2_r,
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hsp_1_int_ie3_r,
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hsp_1_int_ie4_r,
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hsp_1_int_ie5_r,
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hsp_1_int_ie6_r,
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hsp_1_int_ie7_r,
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},
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};
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/**
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* hsp_int_ie_regs is a 1D array of read-only pointers to a
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* function returning u32.
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*
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* Array of functions that retrun addresses of hsp IR
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* regs in DCE cluster based on the id.
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*/
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static u32 (*const hsp_int_ir_regs[DCE_MAX_HSP_T264])(void) = {
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[0U] = hsp_0_int_ir_r,
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[1U] = hsp_1_int_ir_r,
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};
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/**
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* dce_hsp_ie_read_t264 - Read the u32 value from hsp_int_ie#n
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* in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @hsp_id : ID of hsp instance used
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* @id : Shared IE Id.
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*
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* Return : actual value if successful, 0xffffffff for errors scenarios
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*/
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u32 dce_hsp_ie_read_t264(struct tegra_dce *d, u8 hsp_id, u8 id)
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{
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if (id >= DCE_MAX_HSP_IE_T264 || hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid Shared HSP IE ID:%u or hsp:%u", id, hsp_id);
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return 0xffffffff; /* TODO : Add DCE Error Numbers */
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}
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return dce_readl(d, hsp_int_ie_regs[hsp_id][id]());
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}
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/**
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* dce_hsp_ie_write_t264 - Read the u32 value from hsp_int_ie#n
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* in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @val : Value to be written
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* @hsp_id : ID of hsp instance used
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* @id : Shared IE Id.
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*
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* Return : void
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*/
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void dce_hsp_ie_write_t264(struct tegra_dce *d, u32 val, u8 hsp_id, u8 id)
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{
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if (id >= DCE_MAX_HSP_IE_T264 || hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid Shared HSP IE ID:%u or hsp:%u", id, hsp_id);
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return;
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}
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dce_writel(d, hsp_int_ie_regs[hsp_id][id](),
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val | dce_readl(d, hsp_int_ie_regs[hsp_id][id]()));
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}
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/**
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* dce_hsp_ir_read_t264 - Read the u32 value from hsp_int_ir
|
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* in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @hsp_id : ID of hsp instance used
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*
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* Return : actual value if successful, 0xffffffff for errors scenarios
|
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*/
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u32 dce_hsp_ir_read_t264(struct tegra_dce *d, u8 hsp_id)
|
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{
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if (hsp_id >= DCE_MAX_HSP_T264) {
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dce_err(d, "Invalid HSP ID:%u", hsp_id);
|
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return 0xffffffff; /* TODO : Add DCE Error Numbers */
|
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}
|
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return dce_readl(d, hsp_int_ir_regs[hsp_id]());
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}
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167
drivers/platform/tegra/dce/dce-hsp-ss-t264.c
Normal file
167
drivers/platform/tegra/dce/dce-hsp-ss-t264.c
Normal file
@@ -0,0 +1,167 @@
|
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/*
|
||||
* Copyright (c) 2023-2024, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#include <dce.h>
|
||||
#include <dce-util-common.h>
|
||||
#include <hw/t264/hw_hsp_dce.h>
|
||||
#include <dce-hsp-t264.h>
|
||||
|
||||
/**
|
||||
* ss_set_regs is a 2D array of read-only pointers to a function returning u32.
|
||||
*
|
||||
* Array of functions that retrun base addresses of shared semaphores set
|
||||
* registers in DCE cluster based on the semaphore id and HSP id.
|
||||
*/
|
||||
static u32 (*const ss_set_regs[DCE_MAX_HSP_T264][DCE_MAX_NO_SS_T264])(void) = {
|
||||
[0U] = {
|
||||
hsp_0_ss0_set_r,
|
||||
hsp_0_ss1_set_r,
|
||||
hsp_0_ss2_set_r,
|
||||
hsp_0_ss3_set_r,
|
||||
},
|
||||
[1U] = {
|
||||
hsp_1_ss0_set_r,
|
||||
hsp_1_ss1_set_r,
|
||||
hsp_1_ss2_set_r,
|
||||
hsp_1_ss3_set_r,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* ss_clear_regs is a 2D array of read-only pointers to a function
|
||||
* returning u32.
|
||||
*
|
||||
* Array of functions that retrun base addresses of shared semaphores clear
|
||||
* registers in DCE cluster based on the semaphore id and HSP id.
|
||||
*/
|
||||
static u32 (*const ss_clear_regs[DCE_MAX_HSP_T264][DCE_MAX_NO_SS_T264])(void) = {
|
||||
[0U] = {
|
||||
hsp_0_ss0_clr_r,
|
||||
hsp_0_ss1_clr_r,
|
||||
hsp_0_ss2_clr_r,
|
||||
hsp_0_ss3_clr_r,
|
||||
},
|
||||
[1U] = {
|
||||
hsp_1_ss0_clr_r,
|
||||
hsp_1_ss1_clr_r,
|
||||
hsp_1_ss2_clr_r,
|
||||
hsp_1_ss3_clr_r,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* ss_state_regs is a 2D array of read-only pointers to a function
|
||||
* returning u32.
|
||||
*
|
||||
* Array of functions that retrun base addresses of shared semaphores state
|
||||
* registers in DCE cluster based on the semaphore id and HSP id.
|
||||
*/
|
||||
static u32 (*const ss_state_regs[DCE_MAX_HSP_T264][DCE_MAX_NO_SS_T264])(void) = {
|
||||
[0U] = {
|
||||
hsp_0_ss0_state_r,
|
||||
hsp_0_ss1_state_r,
|
||||
hsp_0_ss2_state_r,
|
||||
hsp_0_ss3_state_r,
|
||||
},
|
||||
[1U] = {
|
||||
hsp_1_ss0_state_r,
|
||||
hsp_1_ss1_state_r,
|
||||
hsp_1_ss2_state_r,
|
||||
hsp_1_ss3_state_r,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* dce_ss_get_state_t264 - Get the state of ss_#n in the DCE Cluster
|
||||
*
|
||||
* @d : Pointer to tegra_dce struct.
|
||||
* @hsp_id : ID of hsp instance used
|
||||
* @id : Shared Semaphore Id.
|
||||
*
|
||||
* Return : u32
|
||||
*/
|
||||
u32 dce_ss_get_state_t264(struct tegra_dce *d, u8 hsp_id, u8 id)
|
||||
{
|
||||
return dce_readl(d, ss_state_regs[hsp_id][id]());
|
||||
}
|
||||
|
||||
/**
|
||||
* dce_ss_set_t264 - Set an u32 value to ss_#n in the DCE Cluster
|
||||
*
|
||||
* @d : Pointer to tegra_dce struct.
|
||||
* @bpos : bit to be set.
|
||||
* @hsp_id : ID of hsp instance used
|
||||
* @id : Shared Semaphore Id.
|
||||
*
|
||||
* Return : Void
|
||||
*/
|
||||
void dce_ss_set_t264(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id)
|
||||
{
|
||||
unsigned long val = 0U;
|
||||
|
||||
if (hsp_id >= DCE_MAX_HSP_T264 || id >= DCE_MAX_NO_SS_T264) {
|
||||
dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp_id, id);
|
||||
return;
|
||||
}
|
||||
|
||||
val = dce_ss_get_state_t264(d, d->hsp_id, id);
|
||||
|
||||
/**
|
||||
* Debug info. please remove
|
||||
*/
|
||||
dce_info(d, "Current Value in SS#%d : %lx", id, val);
|
||||
|
||||
/**
|
||||
* TODO :Use DCE_INSERT here.
|
||||
*/
|
||||
dce_bitmap_set(&val, bpos, 1);
|
||||
|
||||
/**
|
||||
* Debug info. please remove
|
||||
*/
|
||||
dce_info(d, "Value after bitmap operation : %lx", val);
|
||||
|
||||
dce_writel(d, ss_set_regs[hsp_id][id](), (u32)val);
|
||||
|
||||
/**
|
||||
* Debug info. please remove
|
||||
*/
|
||||
val = dce_ss_get_state_t264(d, d->hsp_id, id);
|
||||
dce_info(d, "Current Value in SS#%d : %lx", id, val);
|
||||
}
|
||||
|
||||
/**
|
||||
* dce_ss_clear_t264 - Clear a bit in ss_#n in the DCE Cluster
|
||||
*
|
||||
* @d : Pointer to tegra_dce struct.
|
||||
* @bpos : bit to be cleared.
|
||||
* @hsp_id : ID of hsp instance used
|
||||
* @id : Shared Semaphore Id.
|
||||
*
|
||||
* Return : Void
|
||||
*/
|
||||
void dce_ss_clear_t264(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
if (hsp_id >= DCE_MAX_HSP_T264 || id >= DCE_MAX_NO_SS_T264) {
|
||||
dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp_id, id);
|
||||
return;
|
||||
}
|
||||
|
||||
val = dce_ss_get_state_t264(d, d->hsp_id, id);
|
||||
|
||||
dce_bitmap_set(&val, bpos, 1);
|
||||
|
||||
dce_writel(d, ss_clear_regs[hsp_id][id](), val);
|
||||
}
|
||||
@@ -26,6 +26,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/device.h>
|
||||
#include <dce-hsp-t234.h>
|
||||
#include <dce-hsp-t264.h>
|
||||
|
||||
/**
|
||||
* The following platform info is needed for backdoor
|
||||
@@ -43,11 +44,22 @@ static const struct dce_platform_data t234_dce_platform_data = {
|
||||
.use_physical_id = false,
|
||||
};
|
||||
|
||||
__weak const struct of_device_id tegra_dce_of_match[] = {
|
||||
static const struct dce_platform_data t264_dce_platform_data = {
|
||||
.stream_id = 0x0,
|
||||
.hsp_id = 0x0,
|
||||
.fw_info_valid = false,
|
||||
.use_physical_id = false,
|
||||
};
|
||||
|
||||
const struct of_device_id tegra_dce_of_match[] = {
|
||||
{
|
||||
.compatible = "nvidia,tegra234-dce",
|
||||
.data = (struct dce_platform_data *)&t234_dce_platform_data
|
||||
},
|
||||
{
|
||||
.compatible = "nvidia,tegra264-dce",
|
||||
.data = (struct dce_platform_data *)&t264_dce_platform_data
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_dce_of_match);
|
||||
@@ -221,6 +233,9 @@ static int dce_init_hsp_hal_fn(struct platform_device *pdev,
|
||||
if (of_device_is_compatible(node, "nvidia,tegra234-dce")) {
|
||||
dev_info(&pdev->dev, "Setting DCE HSP functions for tegra234-dce");
|
||||
DCE_HSP_INIT_T234(d->hsp);
|
||||
} else if (of_device_is_compatible(node, "nvidia,tegra264-dce")) {
|
||||
dev_info(&pdev->dev, "Setting DCE HSP functions for tegra234-dce");
|
||||
DCE_HSP_INIT_T264(d->hsp);
|
||||
} else {
|
||||
ret = -1;
|
||||
dev_err(&pdev->dev, "DCE SOC not supported");
|
||||
|
||||
54
drivers/platform/tegra/dce/include/dce-hsp-t264.h
Normal file
54
drivers/platform/tegra/dce/include/dce-hsp-t264.h
Normal file
@@ -0,0 +1,54 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef DCE_HSP_T264_H
|
||||
#define DCE_HSP_T264_H
|
||||
|
||||
#include <linux/types.h> // TODO: use dce-types
|
||||
|
||||
struct tegra_dce;
|
||||
|
||||
#define DCE_MAX_HSP_T264 2
|
||||
#define DCE_MAX_NO_SS_T264 4
|
||||
#define DCE_MAX_NO_SMB_T264 8
|
||||
#define DCE_MAX_HSP_IE_T264 8
|
||||
|
||||
/**
|
||||
* DCE HSP Shared Semaphore Utility functions. Description
|
||||
* can be found with function definitions.
|
||||
*/
|
||||
u32 dce_ss_get_state_t264(struct tegra_dce *d, u8 hsp_id, u8 id);
|
||||
void dce_ss_set_t264(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id);
|
||||
void dce_ss_clear_t264(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id);
|
||||
|
||||
/**
|
||||
* DCE HSP Shared Mailbox Utility functions. Description
|
||||
* can be found with function definitions.
|
||||
*/
|
||||
void dce_smb_set_t264(struct tegra_dce *d, u32 val, u8 hsp_id, u8 id);
|
||||
void dce_smb_set_full_ie_t264(struct tegra_dce *d, bool en, u8 hsp_id, u8 id);
|
||||
u32 dce_smb_read_full_ie_t264(struct tegra_dce *d, u8 hsp_id, u8 id);
|
||||
void dce_smb_set_empty_ie_t264(struct tegra_dce *d, bool en, u8 hsp_id, u8 id);
|
||||
u32 dce_smb_read_t264(struct tegra_dce *d, u8 hsp_id, u8 id);
|
||||
u32 dce_hsp_ie_read_t264(struct tegra_dce *d, u8 hsp_id, u8 id);
|
||||
void dce_hsp_ie_write_t264(struct tegra_dce *d, u32 val, u8 hsp_id, u8 id);
|
||||
u32 dce_hsp_ir_read_t264(struct tegra_dce *d, u8 hsp_id);
|
||||
|
||||
#define DCE_HSP_INIT_T264(hsp) \
|
||||
({ \
|
||||
hsp.ss_get_state = dce_ss_get_state_t264; \
|
||||
hsp.ss_set = dce_ss_set_t264; \
|
||||
hsp.ss_clear = dce_ss_clear_t264; \
|
||||
hsp.smb_set = dce_smb_set_t264; \
|
||||
hsp.smb_set_full_ie = dce_smb_set_full_ie_t264; \
|
||||
hsp.smb_read_full_ie = dce_smb_read_full_ie_t264; \
|
||||
hsp.smb_set_empty_ie = dce_smb_set_empty_ie_t264; \
|
||||
hsp.smb_read = dce_smb_read_t264; \
|
||||
hsp.hsp_ie_read = dce_hsp_ie_read_t264; \
|
||||
hsp.hsp_ie_write = dce_hsp_ie_write_t264; \
|
||||
hsp.hsp_ir_read = dce_hsp_ir_read_t264; \
|
||||
})
|
||||
|
||||
#endif
|
||||
413
drivers/platform/tegra/dce/include/hw/t264/hw_hsp_dce.h
Normal file
413
drivers/platform/tegra/dce/include/hw/t264/hw_hsp_dce.h
Normal file
@@ -0,0 +1,413 @@
|
||||
/*
|
||||
* Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
/*
|
||||
* Function/Macro naming determines intended use:
|
||||
*
|
||||
* <x>_r(void) : Returns the offset for register <x>.
|
||||
*
|
||||
* <x>_o(void) : Returns the offset for element <x>.
|
||||
*
|
||||
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
|
||||
*
|
||||
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
|
||||
*
|
||||
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
|
||||
* and masked to place it at field <y> of register <x>. This value
|
||||
* can be |'d with others to produce a full register value for
|
||||
* register <x>.
|
||||
*
|
||||
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
|
||||
* value can be ~'d and then &'d to clear the value of field <y> for
|
||||
* register <x>.
|
||||
*
|
||||
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
|
||||
* to place it at field <y> of register <x>. This value can be |'d
|
||||
* with others to produce a full register value for <x>.
|
||||
*
|
||||
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
|
||||
* <x> value 'r' after being shifted to place its LSB at bit 0.
|
||||
* This value is suitable for direct comparison with other unshifted
|
||||
* values appropriate for use in field <y> of register <x>.
|
||||
*
|
||||
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
|
||||
* field <y> of register <x>. This value is suitable for direct
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef DCE_HW_HSP_DCE_H
|
||||
#define DCE_HW_HSP_DCE_H
|
||||
|
||||
static inline u32 hsp_0_int_ie0_r(void)
|
||||
{
|
||||
return 0x100100U;
|
||||
}
|
||||
static inline u32 hsp_0_int_ie1_r(void)
|
||||
{
|
||||
return 0x100104U;
|
||||
}
|
||||
static inline u32 hsp_0_int_ie2_r(void)
|
||||
{
|
||||
return 0x100108U;
|
||||
}
|
||||
static inline u32 hsp_0_int_ie3_r(void)
|
||||
{
|
||||
return 0x10010cU;
|
||||
}
|
||||
static inline u32 hsp_0_int_ie4_r(void)
|
||||
{
|
||||
return 0x100110U;
|
||||
}
|
||||
static inline u32 hsp_0_int_ie5_r(void)
|
||||
{
|
||||
return 0x100114U;
|
||||
}
|
||||
static inline u32 hsp_0_int_ie6_r(void)
|
||||
{
|
||||
return 0x100118U;
|
||||
}
|
||||
static inline u32 hsp_0_int_ie7_r(void)
|
||||
{
|
||||
return 0x10011cU;
|
||||
}
|
||||
static inline u32 hsp_0_int_ir_r(void)
|
||||
{
|
||||
return 0x100304U;
|
||||
}
|
||||
static inline u32 hsp_0_sm0_r(void)
|
||||
{
|
||||
return 0x110000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm0_full_int_ie_r(void)
|
||||
{
|
||||
return 0x110004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm0_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x110008U;
|
||||
}
|
||||
static inline u32 hsp_0_sm1_r(void)
|
||||
{
|
||||
return 0x118000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm1_full_int_ie_r(void)
|
||||
{
|
||||
return 0x118004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm1_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x118008U;
|
||||
}
|
||||
static inline u32 hsp_0_sm2_r(void)
|
||||
{
|
||||
return 0x120000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm2_full_int_ie_r(void)
|
||||
{
|
||||
return 0x120004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm2_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x120008U;
|
||||
}
|
||||
static inline u32 hsp_0_sm3_r(void)
|
||||
{
|
||||
return 0x128000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm3_full_int_ie_r(void)
|
||||
{
|
||||
return 0x128004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm3_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x128008U;
|
||||
}
|
||||
static inline u32 hsp_0_sm4_r(void)
|
||||
{
|
||||
return 0x130000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm4_full_int_ie_r(void)
|
||||
{
|
||||
return 0x130004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm4_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x130008U;
|
||||
}
|
||||
static inline u32 hsp_0_sm5_r(void)
|
||||
{
|
||||
return 0x138000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm5_full_int_ie_r(void)
|
||||
{
|
||||
return 0x138004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm5_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x138008U;
|
||||
}
|
||||
static inline u32 hsp_0_sm6_r(void)
|
||||
{
|
||||
return 0x140000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm6_full_int_ie_r(void)
|
||||
{
|
||||
return 0x140004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm6_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x140008U;
|
||||
}
|
||||
static inline u32 hsp_0_sm7_r(void)
|
||||
{
|
||||
return 0x148000U;
|
||||
}
|
||||
static inline u32 hsp_0_sm7_full_int_ie_r(void)
|
||||
{
|
||||
return 0x148004U;
|
||||
}
|
||||
static inline u32 hsp_0_sm7_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x148008U;
|
||||
}
|
||||
static inline u32 hsp_0_ss0_state_r(void)
|
||||
{
|
||||
return 0x150000U;
|
||||
}
|
||||
static inline u32 hsp_0_ss0_set_r(void)
|
||||
{
|
||||
return 0x150004U;
|
||||
}
|
||||
static inline u32 hsp_0_ss0_clr_r(void)
|
||||
{
|
||||
return 0x150008U;
|
||||
}
|
||||
static inline u32 hsp_0_ss1_state_r(void)
|
||||
{
|
||||
return 0x160000U;
|
||||
}
|
||||
static inline u32 hsp_0_ss1_set_r(void)
|
||||
{
|
||||
return 0x160004U;
|
||||
}
|
||||
static inline u32 hsp_0_ss1_clr_r(void)
|
||||
{
|
||||
return 0x160008U;
|
||||
}
|
||||
static inline u32 hsp_0_ss2_state_r(void)
|
||||
{
|
||||
return 0x170000U;
|
||||
}
|
||||
static inline u32 hsp_0_ss2_set_r(void)
|
||||
{
|
||||
return 0x170004U;
|
||||
}
|
||||
static inline u32 hsp_0_ss2_clr_r(void)
|
||||
{
|
||||
return 0x170008U;
|
||||
}
|
||||
static inline u32 hsp_0_ss3_state_r(void)
|
||||
{
|
||||
return 0x180000U;
|
||||
}
|
||||
static inline u32 hsp_0_ss3_set_r(void)
|
||||
{
|
||||
return 0x180004U;
|
||||
}
|
||||
static inline u32 hsp_0_ss3_clr_r(void)
|
||||
{
|
||||
return 0x180008U;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie0_r(void)
|
||||
{
|
||||
return 0x200100U;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie1_r(void)
|
||||
{
|
||||
return 0x200104U;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie2_r(void)
|
||||
{
|
||||
return 0x200108U;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie3_r(void)
|
||||
{
|
||||
return 0x20010cU;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie4_r(void)
|
||||
{
|
||||
return 0x200110U;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie5_r(void)
|
||||
{
|
||||
return 0x200114U;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie6_r(void)
|
||||
{
|
||||
return 0x200118U;
|
||||
}
|
||||
static inline u32 hsp_1_int_ie7_r(void)
|
||||
{
|
||||
return 0x20011cU;
|
||||
}
|
||||
static inline u32 hsp_1_int_ir_r(void)
|
||||
{
|
||||
return 0x200304U;
|
||||
}
|
||||
static inline u32 hsp_1_sm0_r(void)
|
||||
{
|
||||
return 0x210000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm0_full_int_ie_r(void)
|
||||
{
|
||||
return 0x210004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm0_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x210008U;
|
||||
}
|
||||
static inline u32 hsp_1_sm1_r(void)
|
||||
{
|
||||
return 0x218000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm1_full_int_ie_r(void)
|
||||
{
|
||||
return 0x218004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm1_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x218008U;
|
||||
}
|
||||
static inline u32 hsp_1_sm2_r(void)
|
||||
{
|
||||
return 0x220000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm2_full_int_ie_r(void)
|
||||
{
|
||||
return 0x220004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm2_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x220008U;
|
||||
}
|
||||
static inline u32 hsp_1_sm3_r(void)
|
||||
{
|
||||
return 0x228000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm3_full_int_ie_r(void)
|
||||
{
|
||||
return 0x228004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm3_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x228008U;
|
||||
}
|
||||
static inline u32 hsp_1_sm4_r(void)
|
||||
{
|
||||
return 0x230000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm4_full_int_ie_r(void)
|
||||
{
|
||||
return 0x230004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm4_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x230008U;
|
||||
}
|
||||
static inline u32 hsp_1_sm5_r(void)
|
||||
{
|
||||
return 0x238000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm5_full_int_ie_r(void)
|
||||
{
|
||||
return 0x238004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm5_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x238008U;
|
||||
}
|
||||
static inline u32 hsp_1_sm6_r(void)
|
||||
{
|
||||
return 0x240000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm6_full_int_ie_r(void)
|
||||
{
|
||||
return 0x240004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm6_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x240008U;
|
||||
}
|
||||
static inline u32 hsp_1_sm7_r(void)
|
||||
{
|
||||
return 0x248000U;
|
||||
}
|
||||
static inline u32 hsp_1_sm7_full_int_ie_r(void)
|
||||
{
|
||||
return 0x248004U;
|
||||
}
|
||||
static inline u32 hsp_1_sm7_empty_int_ie_r(void)
|
||||
{
|
||||
return 0x248008U;
|
||||
}
|
||||
static inline u32 hsp_1_ss0_state_r(void)
|
||||
{
|
||||
return 0x250000U;
|
||||
}
|
||||
static inline u32 hsp_1_ss0_set_r(void)
|
||||
{
|
||||
return 0x250004U;
|
||||
}
|
||||
static inline u32 hsp_1_ss0_clr_r(void)
|
||||
{
|
||||
return 0x250008U;
|
||||
}
|
||||
static inline u32 hsp_1_ss1_state_r(void)
|
||||
{
|
||||
return 0x260000U;
|
||||
}
|
||||
static inline u32 hsp_1_ss1_set_r(void)
|
||||
{
|
||||
return 0x260004U;
|
||||
}
|
||||
static inline u32 hsp_1_ss1_clr_r(void)
|
||||
{
|
||||
return 0x260008U;
|
||||
}
|
||||
static inline u32 hsp_1_ss2_state_r(void)
|
||||
{
|
||||
return 0x270000U;
|
||||
}
|
||||
static inline u32 hsp_1_ss2_set_r(void)
|
||||
{
|
||||
return 0x270004U;
|
||||
}
|
||||
static inline u32 hsp_1_ss2_clr_r(void)
|
||||
{
|
||||
return 0x270008U;
|
||||
}
|
||||
static inline u32 hsp_1_ss3_state_r(void)
|
||||
{
|
||||
return 0x280000U;
|
||||
}
|
||||
static inline u32 hsp_1_ss3_set_r(void)
|
||||
{
|
||||
return 0x280004U;
|
||||
}
|
||||
static inline u32 hsp_1_ss3_clr_r(void)
|
||||
{
|
||||
return 0x280008U;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user