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serializer: mask branch sink count change events

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When ruining a few hundred loops of link training between the SOC
and the serializer, we are seeing unexpected HPD_IRQ being triggered
by the MAX96745/96851 serializers due to "Branch sink count change"
event. Till we figure out why this is happening, disable this
interrupt source.

Bug 3676822

Change-Id: Id56ff7d324b9a51f5468afb2d74df7856040056d
Signed-off-by: Yogish Kulkarni <yogishk@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2758859
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Yogish Kulkarni
2022-08-09 18:17:23 +05:30
committed by Laxman Dewangan
parent 90579e82d5
commit 9d71b422fc
1 changed files with 14 additions and 0 deletions
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14
drivers/video/tegra/dc/bridge/maxim_gmsl_dp_serializer.c
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@@ -87,6 +87,10 @@
#define MAX_GMSL_DP_SER_MISC_CONFIG_B1 0x7019
#define MAX_GMSL_DP_SER_MISC_CONFIG_B1_MASK (1 << 0)
#define MAX_GMSL_DP_SER_MISC_CONFIG_B1_VAL 0x1
#define MAX_GMSL_DP_SER_HPD_INTERRUPT_MASK 0x702D
#define MAX_GMSL_DP_SER_HPD_BRANCH_SINK_COUNT_CHANGE_INTERRUPT_DISABLE_VAL 0x20
#define MAX_GMSL_DP_SER_MAX_LINK_COUNT 0x7070
#define MAX_GMSL_DP_SER_MAX_LINK_RATE 0x7074
@@ -227,6 +231,16 @@ static void max_gmsl_dp_ser_setup(struct max_gmsl_dp_ser_priv *priv)
MAX_GMSL_DP_SER_VID_TX_U,
};
/*
* WAR: When ruining a few hundred loops of link training between the
* SOC and the serializer, we are seeing unexpected HPD_IRQ being
* triggered by the MAX96745/96851 serializers due to "Branch sink count
* change" event. Till we figure out why this is happening, disable this
* interrupt source.
*/
max_gmsl_dp_ser_write(priv, MAX_GMSL_DP_SER_HPD_INTERRUPT_MASK,
MAX_GMSL_DP_SER_HPD_BRANCH_SINK_COUNT_CHANGE_INTERRUPT_DISABLE_VAL);
max_gmsl_dp_ser_write(priv, MAX_GMSL_DP_SER_PHY_EDP_0_CTRL0_B0, 0x0f);
max_gmsl_dp_ser_write(priv, MAX_GMSL_DP_SER_PHY_EDP_0_CTRL0_B1, 0x0f);
max_gmsl_dp_ser_write(priv, MAX_GMSL_DP_SER_PHY_EDP_1_CTRL0_B0, 0x0f);