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git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-25 10:42:21 +03:00
nvadsp: Modularize chip specific structures
For easy of extensibility to future chips, below data and functions applicable to T23x are moved to dev-t18x.c - chip data for supported chips - set_boot_vec: set up EVP - set_boot_freqs: set ADSP freq as per DT property - check_wfi_status: check WFI status from AMISC - dump_core_state: ADSP core and state dump Bug 3682950 Change-Id: Iffba56addc9a68ec33de390a379fe725e727cfad Signed-off-by: Viswanath L <viswanathl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3107450 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
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Viswanath L
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/**
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* Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2015-2024, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/version.h>
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@@ -21,6 +21,22 @@
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#include "dev.h"
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#include "dev-t18x.h"
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#include "amisc.h"
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#include "amc.h"
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#include "adsp_shared_struct.h"
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#include "hwmailbox.h"
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#include "log_state.h"
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/* macros used to find the current mode of ADSP */
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#define MODE_MASK 0x1f
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#define MODE_USR 0x10
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_MON 0x16
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#define MODE_ABT 0x17
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#define MODE_UND 0x1b
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#define MODE_SYS 0x1f
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#ifdef CONFIG_PM
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static int nvadsp_t18x_clocks_disable(struct platform_device *pdev)
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@@ -135,7 +151,7 @@ static int __nvadsp_t18x_runtime_idle(struct device *dev)
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return 0;
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}
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int nvadsp_pm_t18x_init(struct platform_device *pdev)
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static int nvadsp_pm_t18x_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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@@ -150,6 +166,323 @@ int nvadsp_pm_t18x_init(struct platform_device *pdev)
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}
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#endif /* CONFIG_PM */
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static void print_arm_mode_regs(struct nvadsp_drv_data *drv_data)
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{
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struct nvadsp_exception_context *excep_context;
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struct arm_fault_frame_shared *shared_frame;
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struct arm_mode_regs_shared *shared_regs;
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struct nvadsp_shared_mem *shared_mem;
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struct device *dev = &drv_data->pdev->dev;
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shared_mem = drv_data->shared_adsp_os_data;
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excep_context = &shared_mem->exception_context;
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shared_frame = &excep_context->frame;
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shared_regs = &excep_context->regs;
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dev_err(dev, "dumping arm mode register data...\n");
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dev_err(dev, "%c fiq r13 0x%08x r14 0x%08x\n",
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((shared_frame->spsr & MODE_MASK) == MODE_FIQ) ? '*' : ' ',
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shared_regs->fiq_r13, shared_regs->fiq_r14);
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dev_err(dev, "%c irq r13 0x%08x r14 0x%08x\n",
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((shared_frame->spsr & MODE_MASK) == MODE_IRQ) ? '*' : ' ',
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shared_regs->irq_r13, shared_regs->irq_r14);
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dev_err(dev, "%c svc r13 0x%08x r14 0x%08x\n",
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((shared_frame->spsr & MODE_MASK) == MODE_SVC) ? '*' : ' ',
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shared_regs->svc_r13, shared_regs->svc_r14);
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dev_err(dev, "%c und r13 0x%08x r14 0x%08x\n",
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((shared_frame->spsr & MODE_MASK) == MODE_UND) ? '*' : ' ',
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shared_regs->und_r13, shared_regs->und_r14);
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dev_err(dev, "%c sys r13 0x%08x r14 0x%08x\n",
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((shared_frame->spsr & MODE_MASK) == MODE_SYS) ? '*' : ' ',
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shared_regs->sys_r13, shared_regs->sys_r14);
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dev_err(dev, "%c abt r13 0x%08x r14 0x%08x\n",
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((shared_frame->spsr & MODE_MASK) == MODE_ABT) ? '*' : ' ',
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shared_regs->abt_r13, shared_regs->abt_r14);
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}
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static void print_arm_fault_frame(struct nvadsp_drv_data *drv_data)
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{
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struct nvadsp_exception_context *excep_context;
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struct arm_fault_frame_shared *shared_frame;
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struct nvadsp_shared_mem *shared_mem;
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struct device *dev = &drv_data->pdev->dev;
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shared_mem = drv_data->shared_adsp_os_data;
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excep_context = &shared_mem->exception_context;
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shared_frame = &excep_context->frame;
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dev_err(dev, "dumping fault frame...\n");
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dev_err(dev, "r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n",
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shared_frame->r[0], shared_frame->r[1], shared_frame->r[2],
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shared_frame->r[3]);
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dev_err(dev, "r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
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shared_frame->r[4], shared_frame->r[5], shared_frame->r[6],
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shared_frame->r[7]);
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dev_err(dev, "r8 0x%08x r9 0x%08x r10 0x%08x r11 0x%08x\n",
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shared_frame->r[8], shared_frame->r[9], shared_frame->r[10],
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shared_frame->r[11]);
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dev_err(dev, "r12 0x%08x usp 0x%08x ulr 0x%08x pc 0x%08x\n",
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shared_frame->r[12], shared_frame->usp, shared_frame->ulr,
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shared_frame->pc);
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dev_err(dev, "spsr 0x%08x\n", shared_frame->spsr);
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}
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static void dump_thread_name(struct platform_device *pdev, u32 val)
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{
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dev_info(&pdev->dev, "%s: adsp current thread: %c%c%c%c\n",
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__func__,
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(val >> 24) & 0xFF, (val >> 16) & 0xFF,
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(val >> 8) & 0xFF, (val >> 0) & 0xFF);
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}
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static void dump_irq_num(struct platform_device *pdev, u32 val)
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{
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dev_info(&pdev->dev, "%s: adsp current/last irq : %d\n",
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__func__, val);
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}
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static void get_adsp_state(struct nvadsp_drv_data *drv_data)
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{
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struct device *dev;
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uint32_t val;
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const char *msg;
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if (!drv_data->pdev) {
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pr_err("ADSP Driver is not initialized\n");
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return;
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}
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dev = &drv_data->pdev->dev;
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if (drv_data->chip_data->adsp_state_hwmbox == 0) {
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dev_info(dev, "%s: No state hwmbox available\n", __func__);
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return;
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}
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val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_state_hwmbox);
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dev_info(dev, "%s: adsp state hwmbox value: 0x%X\n", __func__, val);
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switch (val) {
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case ADSP_LOADER_MAIN_ENTRY:
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msg = "loader_main: entry to loader_main";
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break;
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case ADSP_LOADER_MAIN_CACHE_DISABLE_COMPLETE:
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msg = "loader_main: Cache has been disabled";
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break;
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case ADSP_LOADER_MAIN_CONFIGURE_MMU_COMPLETE:
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msg = "loader_main: MMU configuration is complete";
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break;
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case ADSP_LOADER_MAIN_CACHE_ENABLE_COMPLETE:
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msg = "loader_main: Cache has been enabled";
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break;
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case ADSP_LOADER_MAIN_FPU_ENABLE_COMPLETE:
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msg = "loader_main: FPU has been enabled";
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break;
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case ADSP_LOADER_MAIN_DECOMPRESSION_COMPLETE:
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msg = "loader_main: ADSP FW decompression is complete";
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break;
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case ADSP_LOADER_MAIN_EXIT:
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msg = "loader_main: exiting loader_main function";
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break;
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case ADSP_START_ENTRY_AT_RESET:
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msg = "start: ADSP is at reset";
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break;
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case ADSP_START_CPU_EARLY_INIT:
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msg = "start: ADSP to do cpu_early_init";
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break;
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case ADSP_START_FIRST_BOOT:
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msg = "start: ADSP is booting for first time,"
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"initializing DATA and clearing BSS";
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break;
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case ADSP_START_LK_MAIN_ENTRY:
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msg = "start: ADSP about to enter lk_main";
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break;
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case ADSP_LK_MAIN_ENTRY:
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msg = "lk_main: entry to lk_main";
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break;
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case ADSP_LK_MAIN_EARLY_THREAD_INIT_COMPLETE:
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msg = "lk_main: early_thread_init has been completed";
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break;
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case ADSP_LK_MAIN_EARLY_ARCH_INIT_COMPLETE:
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msg = "lk_main: early_arch_init has been completed";
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break;
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case ADSP_LK_MAIN_EARLY_PLATFORM_INIT_COMPLETE:
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msg = "lk_main: early_platform_init has been completed";
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break;
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case ADSP_LK_MAIN_EARLY_TARGET_INIT_COMPLETE:
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msg = "lk_main: early_target_init has been completed";
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break;
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case ADSP_LK_MAIN_CONSTRUCTOR_INIT_COMPLETE:
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msg = "lk_main: constructors has been called";
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break;
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case ADSP_LK_MAIN_HEAP_INIT_COMPLETE:
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msg = "lk_main: heap has been initialized";
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break;
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case ADSP_LK_MAIN_KERNEL_INIT_COMPLETE:
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msg = "lk_main: ADSP kernel has been initialized";
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break;
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case ADSP_LK_MAIN_CPU_RESUME_ENTRY:
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msg = "lk_main: ADSP is about to resume from suspend";
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break;
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case ADSP_BOOTSTRAP2_ARCH_INIT_COMPLETE:
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msg = "bootstrap2: ADSP arch_init is complete";
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break;
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case ADSP_BOOTSTRAP2_PLATFORM_INIT_COMPLETE:
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msg = "bootstrap2: platform has been initialized";
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break;
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case ADSP_BOOTSTRAP2_TARGET_INIT_COMPLETE:
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msg = "bootstrap2: target has been initialized";
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break;
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case ADSP_BOOTSTRAP2_APP_MODULE_INIT_COMPLETE:
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msg = "bootstrap2: APP modules initialized";
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break;
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case ADSP_BOOTSTRAP2_APP_INIT_COMPLETE:
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msg = "bootstrap2: APP init is complete";
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break;
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case ADSP_BOOTSTRAP2_STATIC_APP_INIT_COMPLETE:
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msg = "bootstrap2: Static apps has been initialized";
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break;
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case ADSP_BOOTSTRAP2_OS_LOAD_COMPLETE:
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msg = "bootstrap2: ADSP OS successfully loaded";
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break;
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case ADSP_SUSPEND_BEGINS:
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msg = "suspend: begins";
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break;
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case ADSP_SUSPEND_MBX_SEND_COMPLETE:
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msg = "suspend: mbox send complete";
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break;
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case ADSP_SUSPEND_DISABLED_TIMERS:
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msg = "suspend: timers disabled";
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break;
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case ADSP_SUSPEND_DISABLED_INTS:
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msg = "suspend: interrupts disabled";
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break;
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case ADSP_SUSPEND_ARAM_SAVED:
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msg = "suspend: aram saved";
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break;
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case ADSP_SUSPEND_AMC_SAVED:
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msg = "suspend: amc saved";
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break;
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case ADSP_SUSPEND_AMISC_SAVED:
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msg = "suspend: amisc saved";
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break;
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case ADSP_SUSPEND_L1_CACHE_DISABLED:
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msg = "suspend: l1 cache disabled";
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break;
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case ADSP_SUSPEND_L2_CACHE_DISABLED:
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msg = "suspend: l2 cache disabled";
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break;
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case ADSP_RESUME_ADSP:
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msg = "resume: beings";
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break;
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case ADSP_RESUME_AMISC_RESTORED:
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msg = "resume: amisc restored";
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break;
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case ADSP_RESUME_AMC_RESTORED:
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msg = "resume: amc restored";
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break;
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case ADSP_RESUME_ARAM_RESTORED:
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msg = "resume: aram restored";
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break;
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case ADSP_RESUME_COMPLETE:
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msg = "resume: complete";
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break;
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case ADSP_WFI_ENTER:
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msg = "WFI: Entering WFI";
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break;
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case ADSP_WFI_EXIT:
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msg = "WFI: Exiting WFI, Failed to Enter";
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break;
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case ADSP_DFS_MBOX_RECV:
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msg = "DFS: mbox received";
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break;
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case ADSP_DFS_MBOX_SENT:
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msg = "DFS: mbox sent";
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break;
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default:
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msg = "Unrecognized ADSP state!!";
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break;
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}
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dev_info(dev, "%s: %s\n", __func__, msg);
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val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_thread_hwmbox);
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dump_thread_name(drv_data->pdev, val);
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val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_irq_hwmbox);
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dump_irq_num(drv_data->pdev, val);
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}
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static void __dump_core_state_t18x(struct nvadsp_drv_data *drv_data)
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{
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print_arm_fault_frame(drv_data);
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print_arm_mode_regs(drv_data);
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get_adsp_state(drv_data);
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}
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static int __set_boot_vec_t18x(struct nvadsp_drv_data *drv_data)
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{
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struct platform_device *pdev = drv_data->pdev;
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struct device *dev = &pdev->dev;
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void *to = drv_data->state.evp_ptr;
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const void *from = drv_data->state.evp;
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int i, sz = AMC_EVP_SIZE;
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dev_dbg(dev, "Copying EVP...\n");
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for (i = 0; i < sz; i += 4) {
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u32 val = *(u32 *)(from + i);
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writel(val, (void __iomem *)(to + i));
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}
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return 0;
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}
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static int __set_boot_freqs_t18x(struct nvadsp_drv_data *drv_data)
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{
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struct nvadsp_shared_mem *shared_mem = drv_data->shared_adsp_os_data;
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struct nvadsp_os_args *os_args = &shared_mem->os_args;
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struct platform_device *pdev = drv_data->pdev;
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struct device *dev = &pdev->dev;
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unsigned long max_adsp_freq;
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unsigned long adsp_freq;
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int ret = 0;
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if (!drv_data->adsp_clk)
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return -EINVAL;
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adsp_freq = drv_data->adsp_freq_hz; /* in Hz*/
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/* round rate shall be used with adsp parent clk i.e. aclk */
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max_adsp_freq = clk_round_rate(drv_data->aclk_clk, ULONG_MAX);
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/* Set max adsp boot freq */
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if (!adsp_freq)
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adsp_freq = max_adsp_freq;
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/* set rate shall be used with adsp parent clk i.e. aclk */
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ret = clk_set_rate(drv_data->aclk_clk, adsp_freq);
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if (ret) {
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dev_err(dev, "setting adsp_freq:%luHz failed.\n", adsp_freq);
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dev_err(dev, "max_adsp_freq:%luHz\n", max_adsp_freq);
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goto end;
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}
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drv_data->adsp_freq = adsp_freq / 1000; /* adsp_freq in KHz*/
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drv_data->adsp_freq_hz = adsp_freq;
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/* adspos uses os_args->adsp_freq_hz for EDF */
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os_args->adsp_freq_hz = drv_data->adsp_freq_hz;
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end:
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dev_dbg(dev, "adsp cpu freq %luKHz\n",
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clk_get_rate(drv_data->adsp_clk) / 1000);
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return ret;
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}
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static int __assert_t18x_adsp(struct nvadsp_drv_data *d)
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{
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struct platform_device *pdev = d->pdev;
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@@ -262,7 +595,35 @@ static int __virt_deassert_t18x_adsp(struct nvadsp_drv_data *d)
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}
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#endif
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int nvadsp_reset_t18x_init(struct platform_device *pdev)
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static bool __check_wfi_status_t18x(struct nvadsp_drv_data *d)
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{
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int cnt = 0;
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bool wfi_status = true;
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u32 adsp_status;
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/*
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* Check L2_IDLE and L2_CLKSTOPPED in ADSP_STATUS
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* NOTE: Standby mode in ADSP L2CC Power Control
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* register should be enabled for this
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*/
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do {
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adsp_status = amisc_readl(d, AMISC_ADSP_STATUS);
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if ((adsp_status & AMISC_ADSP_L2_IDLE) &&
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(adsp_status & AMISC_ADSP_L2_CLKSTOPPED))
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break;
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cnt++;
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mdelay(1);
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} while (cnt < 5);
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if (cnt >= 5) {
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pr_err("ADSP L2C clock not halted: 0x%x\n", adsp_status);
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wfi_status = false;
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}
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return wfi_status;
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}
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static int nvadsp_dev_t18x_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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@@ -278,6 +639,11 @@ int nvadsp_reset_t18x_init(struct platform_device *pdev)
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}
|
||||
#endif
|
||||
|
||||
d->set_boot_vec = __set_boot_vec_t18x;
|
||||
d->set_boot_freqs = __set_boot_freqs_t18x;
|
||||
d->check_wfi_status = __check_wfi_status_t18x;
|
||||
d->dump_core_state = __dump_core_state_t18x;
|
||||
|
||||
d->assert_adsp = __assert_t18x_adsp;
|
||||
d->deassert_adsp = __deassert_t18x_adsp;
|
||||
d->adspall_rst = devm_reset_control_get(dev, "adspall");
|
||||
@@ -294,3 +660,64 @@ int nvadsp_reset_t18x_init(struct platform_device *pdev)
|
||||
end:
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct nvadsp_chipdata tegrat18x_adsp_chipdata = {
|
||||
.hwmb = {
|
||||
.reg_idx = AHSP,
|
||||
.hwmbox0_reg = 0x00000,
|
||||
.hwmbox1_reg = 0X08000,
|
||||
.hwmbox2_reg = 0X10000,
|
||||
.hwmbox3_reg = 0X18000,
|
||||
.hwmbox4_reg = 0X20000,
|
||||
.hwmbox5_reg = 0X28000,
|
||||
.hwmbox6_reg = 0X30000,
|
||||
.hwmbox7_reg = 0X38000,
|
||||
.empty_int_ie = 0x8,
|
||||
},
|
||||
.adsp_shared_mem_hwmbox = 0x18000, /* HWMBOX3 */
|
||||
.adsp_thread_hwmbox = 0x20000, /* HWMBOX4 */
|
||||
.adsp_os_config_hwmbox = 0X28000, /* HWMBOX5 */
|
||||
.adsp_state_hwmbox = 0x30000, /* HWMBOX6 */
|
||||
.adsp_irq_hwmbox = 0x38000, /* HWMBOX7 */
|
||||
.acast_init = nvadsp_acast_t18x_init,
|
||||
.dev_init = nvadsp_dev_t18x_init,
|
||||
.os_init = nvadsp_os_t18x_init,
|
||||
#ifdef CONFIG_PM
|
||||
.pm_init = nvadsp_pm_t18x_init,
|
||||
#endif
|
||||
|
||||
.amc_err_war = true,
|
||||
.num_irqs = NVADSP_VIRQ_MAX,
|
||||
};
|
||||
|
||||
struct nvadsp_chipdata tegra239_adsp_chipdata = {
|
||||
.hwmb = {
|
||||
.reg_idx = AHSP,
|
||||
.hwmbox0_reg = 0x00000,
|
||||
.hwmbox1_reg = 0X08000,
|
||||
.hwmbox2_reg = 0X10000,
|
||||
.hwmbox3_reg = 0X18000,
|
||||
.hwmbox4_reg = 0X20000,
|
||||
.hwmbox5_reg = 0X28000,
|
||||
.hwmbox6_reg = 0X30000,
|
||||
.hwmbox7_reg = 0X38000,
|
||||
.empty_int_ie = 0x8,
|
||||
},
|
||||
.adsp_shared_mem_hwmbox = 0x18000, /* HWMBOX3 */
|
||||
.adsp_thread_hwmbox = 0x20000, /* HWMBOX4 */
|
||||
.adsp_os_config_hwmbox = 0X28000, /* HWMBOX5 */
|
||||
.adsp_state_hwmbox = 0x30000, /* HWMBOX6 */
|
||||
.adsp_irq_hwmbox = 0x38000, /* HWMBOX7 */
|
||||
.acast_init = nvadsp_acast_t18x_init,
|
||||
.dev_init = nvadsp_dev_t18x_init,
|
||||
.os_init = nvadsp_os_t18x_init,
|
||||
#ifdef CONFIG_PM
|
||||
.pm_init = nvadsp_pm_t18x_init,
|
||||
#endif
|
||||
|
||||
.amc_err_war = false,
|
||||
|
||||
/* Populate Chip ID Major Revision as well */
|
||||
.chipid_ext = 0x9,
|
||||
.num_irqs = NVADSP_VIRQ_MAX,
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user