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ASoC: tegra: Update PLLA base rate for x8KHz

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This change is decided as per Bug (Bug 200702569) and
it will keep the range for all channels within 35MHz.
Adding same change to make automation script to work.

Bug 200683609

Change-Id: Ibba3847133d643c0132e8660a8ae21c7383a8afd
Signed-off-by: sheetal <sheetal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2536432
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Asha Talambedu <atalambedu@nvidia.com>
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
sheetal
2021-05-28 18:29:50 +05:30
committed by Sameer Pujar
parent ae9fe52e1e
commit 9e4c08a7c2
1 changed files with 1 additions and 1 deletions
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2
sound/soc/tegra/tegra_asoc_utils.c
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@@ -26,7 +26,7 @@ enum rate_type {
NUM_RATE_TYPE, NUM_RATE_TYPE,
}; };
unsigned int tegra210_pll_base_rate[NUM_RATE_TYPE] = {338688000, 368640000}; unsigned int tegra210_pll_base_rate[NUM_RATE_TYPE] = {338688000, 368640000};
unsigned int tegra186_pll_base_rate[NUM_RATE_TYPE] = {270950400, 245760000}; unsigned int tegra186_pll_base_rate[NUM_RATE_TYPE] = {270950400, 294912000};
unsigned int default_pll_out_rate[NUM_RATE_TYPE] = {45158400, 49152000}; unsigned int default_pll_out_rate[NUM_RATE_TYPE] = {45158400, 49152000};
int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,