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nvethernet: add reading of PHY delays from DT
PHY delays varies from PHY to PHY, so pass these values from platform DT and read the same Bug 200733771 Change-Id: I720dc1ccd42f0f8bcbe23aeb5100b03948cbd3a1 Signed-off-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2556626 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Revanth Kumar Uppala
parent
0ca9eae1b0
commit
9fd74bdf26
@@ -888,25 +888,25 @@ static void ether_adjust_link(struct net_device *dev)
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* PHY interface mode */
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speed = phydev->speed;
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/* XFI mode = 10G:
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UPHY GBE mode = 10G
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MAC = 10G
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XPCS = 10G
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PHY line side = 10G/5G/2.5G/1G/100M
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XFI mode = 5G:
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UPHY GBE mode = 5G
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MAC = 5G
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XPCS = 5G
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PHY line side = 10G/5G/2.5G/1G/100M
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USXGMII mode = 10G:
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UPHY GBE mode = 10G
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MAC = 10G/5G/2.5G (same as PHY line speed)
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XPCS = 10G
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PHY line side = 10G/5G/2.5G
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USXGMII mode = 5G:
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UPHY GBE mode = 5G
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MAC = 5G/2.5G ( same as PHY line speed)
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XPCS = 5G
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PHY line side = 5G/2.5G
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* UPHY GBE mode = 10G
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* MAC = 10G
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* XPCS = 10G
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* PHY line side = 10G/5G/2.5G/1G/100M
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* XFI mode = 5G:
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* UPHY GBE mode = 5G
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* MAC = 5G
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* XPCS = 5G
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* PHY line side = 10G/5G/2.5G/1G/100M
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* USXGMII mode = 10G:
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* UPHY GBE mode = 10G
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* MAC = 10G/5G/2.5G (same as PHY line speed)
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* XPCS = 10G
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* PHY line side = 10G/5G/2.5G
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* USXGMII mode = 5G:
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* UPHY GBE mode = 5G
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* MAC = 5G/2.5G ( same as PHY line speed)
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* XPCS = 5G
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* PHY line side = 5G/2.5G
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*/
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if (pdata->osi_core->mac == OSI_MAC_HW_MGBE) {
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/* MAC and XFI speed should match in XFI mode */
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@@ -2257,8 +2257,10 @@ static int ether_open(struct net_device *dev)
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/* Reset the PHY */
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if (gpio_is_valid(pdata->phy_reset)) {
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gpio_set_value(pdata->phy_reset, 0);
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usleep_range(10, 11);
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usleep_range(pdata->phy_reset_duration,
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pdata->phy_reset_duration + 1);
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gpio_set_value(pdata->phy_reset, 1);
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msleep(pdata->phy_reset_post_delay);
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}
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ether_start_ivc(pdata);
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@@ -4773,8 +4775,10 @@ static int ether_configure_car(struct platform_device *pdev,
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}
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gpio_set_value(pdata->phy_reset, 0);
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usleep_range(10, 11);
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usleep_range(pdata->phy_reset_duration,
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pdata->phy_reset_duration + 1);
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gpio_set_value(pdata->phy_reset, 1);
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msleep(pdata->phy_reset_post_delay);
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}
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ret = ether_get_clks(pdata);
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@@ -4913,11 +4917,11 @@ static int ether_init_plat_resources(struct platform_device *pdev,
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static int ether_parse_phy_dt(struct ether_priv_data *pdata,
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struct device_node *node)
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{
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int err;
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#if KERNEL_VERSION(5, 5, 0) > LINUX_VERSION_CODE
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pdata->interface = of_get_phy_mode(node);
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#else
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int err;
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err = of_get_phy_mode(node, &pdata->interface);
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if (err < 0)
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pr_debug("%s(): phy interface not found\n", __func__);
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@@ -4934,6 +4938,21 @@ static int ether_parse_phy_dt(struct ether_priv_data *pdata,
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break;
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}
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/* Read PHY delays */
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err = of_property_read_u32(pdata->phy_node, "nvidia,phy-rst-duration-usec",
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&pdata->phy_reset_duration);
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if (err < 0) {
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pr_debug("failed to read PHY reset duration,setting to default 10usec\n");
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pdata->phy_reset_duration = 10;
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}
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err = of_property_read_u32(pdata->phy_node, "nvidia,phy-rst-pdelay-msec",
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&pdata->phy_reset_post_delay);
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if (err < 0) {
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pr_debug("failed to read PHY post delay,setting to default 0msec\n");
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pdata->phy_reset_post_delay = 0;
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}
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/* In the case of a fixed PHY, the DT node associated
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* to the PHY is the Ethernet MAC DT node.
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*/
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@@ -5428,14 +5447,15 @@ static int ether_parse_dt(struct ether_priv_data *pdata)
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if ((osi_core->uphy_gbe_mode == OSI_ENABLE) &&
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((osi_core->phy_iface_mode == OSI_XFI_MODE_5G) ||
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(osi_core->phy_iface_mode == OSI_USXGMII_MODE_5G))) {
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dev_err(dev, "Invalid combination of UPHY GBE mode"
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dev_err(dev, "Invalid combination of UPHY 10GBE mode"
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"and XFI/USXGMII 5G mode\n");
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return -EINVAL;
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}
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if ((osi_core->uphy_gbe_mode == OSI_DISABLE) &&
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((osi_core->phy_iface_mode == OSI_XFI_MODE_10G) ||
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(osi_core->phy_iface_mode == OSI_USXGMII_MODE_10G))) {
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dev_err(dev, "Invalid combination of UPHY GBE mode"
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dev_err(dev, "Invalid combination of UPHY 5GBE mode"
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"and XFI/USXGMII 10G mode\n");
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return -EINVAL;
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}
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