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nvethernet: add MGBE monitoring Rx clks

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BPMP-FW exposes the following MGBE RX clocks:
o mgbe0_rx_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_input_m [monitoring clk: virtual clk controls RX clk FMON]
o mgbe0_rx_pcs_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_pcs [mux between mgbe0_rx_pcs_input and mgbe0_tx_pcs]
o mgbe0_rx_pcs_m [monitoring clk: virtual clk controls RX PCS clk FMON]

To enable RX clock FMON -
o Issue clk_set_rate on MGBE_RX_INPUT and MGBE_RX_PCS_INPUT based
on UPHY GBE mode.
o Clk_enable already available on ToT for RX_INPUT_M
and RX_PCS_INPUT_M.

Bug 3288030

Change-Id: Ia71ccc9f21a5e79fecf149efae9032db25af60d8
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2544758
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Bhadram Varka
2021-06-14 17:40:04 +05:30
committed by Revanth Kumar Uppala
parent b02ba38d38
commit 0ca9eae1b0
2 changed files with 57 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

53
drivers/net/ethernet/nvidia/nvethernet/ether_linux.c
View File

@@ -4416,6 +4416,46 @@ static inline void ether_put_clks(struct ether_priv_data *pdata)
}
}
/**
* @brief Set clk rates for mgbe#_rx_input/mgbe#_rx_pcs_input
*
* Algorithm: Sets clk rates based on UPHY GBE mode for
* mgbe#_rx_input/mgbe#_rx_pcs_input clk ID's.
*
* @param[in] pdata: OSD private data.
*
* @retval 0 on success
* @retval "negative value" on failure.
*/
static int ether_set_mgbe_rx_fmon_rates(struct ether_priv_data *pdata)
{
unsigned int uphy_gbe_mode = pdata->osi_core->uphy_gbe_mode;
unsigned long rx_rate, rx_pcs_rate;
int ret;
if (uphy_gbe_mode == OSI_ENABLE) {
rx_rate = ETHER_MGBE_RX_CLK_USXGMII_10G;
rx_pcs_rate = ETHER_MGBE_RX_PCS_CLK_USXGMII_10G;
} else {
rx_rate = ETHER_MGBE_RX_CLK_USXGMII_5G;
rx_pcs_rate = ETHER_MGBE_RX_PCS_CLK_USXGMII_5G;
}
ret = clk_set_rate(pdata->rx_input_clk, rx_rate);
if (ret < 0) {
dev_err(pdata->dev, "failed to set rx_input_clk rate\n");
return ret;
}
ret = clk_set_rate(pdata->rx_pcs_input_clk, rx_pcs_rate);
if (ret < 0) {
dev_err(pdata->dev, "failed to set rx_pcs_input_clk rate\n");
return ret;
}
return 0;
}
/**
* @brief Get MAC MGBE related clocks.
*
@@ -4508,8 +4548,21 @@ static int ether_get_mgbe_clks(struct ether_priv_data *pdata)
goto err_ptp_ref;
}
pdata->rx_input_clk = devm_clk_get(dev, "rx_input");
if (IS_ERR(pdata->rx_input_clk)) {
ret = PTR_ERR(pdata->rx_input_clk);
dev_err(dev, "failed to get rx_input clk\n");
goto err_rx_input;
}
ret = ether_set_mgbe_rx_fmon_rates(pdata);
if (ret < 0)
goto err_rx_input;
return 0;
err_rx_input:
devm_clk_put(dev, pdata->ptp_ref_clk);
err_ptp_ref:
devm_clk_put(dev, pdata->app_clk);
err_app:

4
drivers/net/ethernet/nvidia/nvethernet/ether_linux.h
View File

@@ -111,8 +111,12 @@
// --> link_Tx_clk --> fixed 1/2 gear box divider --> lane TX clk.
#define ETHER_MGBE_TX_CLK_USXGMII_10G 644531250UL
#define ETHER_MGBE_TX_CLK_USXGMII_5G 322265625UL
#define ETHER_MGBE_RX_CLK_USXGMII_10G 644531250UL
#define ETHER_MGBE_RX_CLK_USXGMII_5G 322265625UL
#define ETHER_MGBE_TX_PCS_CLK_USXGMII_10G 156250000UL
#define ETHER_MGBE_TX_PCS_CLK_USXGMII_5G 78125000UL
#define ETHER_MGBE_RX_PCS_CLK_USXGMII_10G 156250000UL
#define ETHER_MGBE_RX_PCS_CLK_USXGMII_5G 78125000UL
#define ETHER_EQOS_TX_CLK_1000M 125000000UL
#define ETHER_EQOS_TX_CLK_100M 25000000UL
#define ETHER_EQOS_TX_CLK_10M 2500000UL