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0ca9eae1b0
BPMP-FW exposes the following MGBE RX clocks: o mgbe0_rx_input [external input clk recovered from GBE UPHY lane] o mgbe0_rx_input_m [monitoring clk: virtual clk controls RX clk FMON] o mgbe0_rx_pcs_input [external input clk recovered from GBE UPHY lane] o mgbe0_rx_pcs [mux between mgbe0_rx_pcs_input and mgbe0_tx_pcs] o mgbe0_rx_pcs_m [monitoring clk: virtual clk controls RX PCS clk FMON] To enable RX clock FMON - o Issue clk_set_rate on MGBE_RX_INPUT and MGBE_RX_PCS_INPUT based on UPHY GBE mode. o Clk_enable already available on ToT for RX_INPUT_M and RX_PCS_INPUT_M. Bug 3288030 Change-Id: Ia71ccc9f21a5e79fecf149efae9032db25af60d8 Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2544758 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit